FDC37B782-NS Standard Microsystems (SMSC), FDC37B782-NS Datasheet - Page 152

• Manufacturer Part Number: FDC37B782-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B782-NS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

PME SUPPORT
The FDC37B78x offers support for PCI power
management
management event is requested by a PCI function
via the assertion of the nPME signal. The
assertion
asynchronous to the PCI clock.
FDC37B78x, active transitions on the ring indicator
inputs nRI1 and nRI2 or the nRING pin, valid NEC
infrared remote control frames, active keyboard-
clock edges, active mouse-clock edges, RTC
alarm, and GPIOs GP10-GP17 can directly assert
the nPME signal. In addition, if the DEVINT_EN bit
in the PME_EN 1 Register is set, and if the
EN_SMI_PME bit in the SMI_EN 2 register is set,
then any of the SMI Events can also generate a
nPME.
diagrams in FIGURE 5 and FIGURE 6.
nPME functionality is controlled by the runtime
registers
<PM1_BLK>+11h.
PME_EN, globally controls PME Wake-up events.
ACPI/PME/SMI REGISTERS
Logical Device A in the configuration section
contains the address pointer to the ACPI power
management register block, and PM1_BLK.
These are run-time registers;
PM1_BLK is an enable bit to allow the SCI group
interrupt to be routed to any serial interrupt or the
IRQ11 pin, or onto the nPME/SCI pin. Note: See
IRQ mux control register for SCI/PME/SMI
selection function and pin configuration bits.
Register Description
The ACPI register model consists of a number of
fixed register blocks that perform designated
functions. A register block consists of a number
of registers that perform Status, Enable and
Control functions. The ACPI specification deals
with events (which have an associated interrupt
status and enable bits, and sometimes an
associated control function) and control features.
The status registers illustrate what defined
function is requesting ACPI interrupt services
See the SCI/PME and SMI/PME logic
and
at
events
deassertion
<PM1_BLK>+Ch
The
(PMEs).
PME
Included in the
of
Enable
nPME
A
through
In the
power
bit,
is
154
When PME_EN is inactive, the nPME signal can
not be asserted. When PME_EN is asserted, any
wake source whose individual PME Wake Enable
register bit is asserted can cause nPME to
become asserted. The PME Wake Status register
indicates which wake source has asserted the
nPME signal. The PME Status bit, PME_STS, is
asserted by active transitions of PME Wake
sources.
independent of the state of the global PME enable,
PME_EN.
In the FDC37B78x the nPME pin is an open drain,
active low, driver. The FDC37B78x nPME pin is
fully isolated from other external devices that might
pull the PCI nPME signal low; i.e., the PCI nPME
signal is capable of being driven high externally by
another active device or pullup even when the the
FDC37B78x VDD is grounded, providing VTR
power is active. The FDC37B78x nPME driver
sinks 6mA at .55V max (see section 4.2.1.1 DC
Specifications, page 122, in the PCI Local Bus
Specification, Revision 2.1).
(SCI). Any status bit in the ACPI specification
has the following attributes:
A.
B.
C.
D.
Note that this implies that if the respective enable
bit is reset and the hardware event occurs, the
respective status bit is set, however no interrupt
is generated until the enable bit is set. This
allows software to test the state of the event (by
examining the status bit) without necessarily
generating an interrupt. There are a special class
of status bits that have no respective enable bit,
Status bits are only set through some
Unless otherwise noted, Status bits are
Status bits only generate interrupts
Function bit positions in the status
defined “hardware event.”
cleared by writing a “HIGH” to that bit
position, and upon VTR POR. Writing a
0 has no effect.
while their associated bit in the enable
register is set.
register have the same bit position in
the
exceptions to this rule, special status
bits have no enables).
PME_STS
enable
will
register
become
(there
asserted
are