M378T2953CZ3-CD5 Samsung Semiconductor, M378T2953CZ3-CD5 Datasheet - Page 7

• Manufacturer Part Number: M378T2953CZ3-CD5
• Manufacturer: Samsung Semiconductor

Specifications of M378T2953CZ3-CD5

• Lead Free Status / RoHS Status: Compliant

7.0 Input/Output Functional Description
UDIMM
RAS, CAS, WE
ODT0-ODT1
DQS0-DQS8
DQS0-DQS8
CKE0-CKE1
DQ0-DQ63
DM0-DM8
CK0-CK2
CK0-CK2
BA0-BA1
CB0-CB7
SA0-SA2
V
V
Symbol
A0-A13
S0-S1
DD
V
DD
V
SDA
SCL
DDQ
REF
,V
SPD
SS
Supply
Supply
Supply
Supply
In/Out
In/Out
In/Out
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge of
CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing)
Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks, CKE
low initiates the Powe Down mode, or the Self-Refresh mode
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the
command decoder is disbled, new command are ignored but previous operations continue. This signal provides for exter-
nal rank selection on systems with multiple ranks
RAS, CAS, and WE (
When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the
Extended Mode Register Set (EMRS).
Reference voltage for SSTL 18 inputs.
Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered
DIMM designs, VDDQ shares the same power plane as VDD pins.
Selects which SDRAM BANK of four is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the colum address, In addition to the column address, AP
is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge
command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to pre-
charge.
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data
during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading.
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to V
these modules.
Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the
DRAMs and DQ8-17 connect to the UDQS pin of the DRAM
These signals and tied at the system planar to either V
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the
SDA bus line to VDD to act as a pullup on the system board.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to VDD to act as a pullup onthe system board.
Power supply for SPD EEPROM. This supply is separate from the V
from 1.7V to 3.6V.
ALONG WITH
CS) define the command being entered.
7 of 24
SS
Function
or V
DD
to configure the serial SPD EERPOM address range.
DD
/V
DDQ
power plane. EEPROM supply is operable
Rev. 1.5 October 2006
DDR2 SDRAM
DD
/V
DDQ
planes on