M378T2953CZ3-CD5 Samsung Semiconductor, M378T2953CZ3-CD5 Datasheet - Page 4

• Manufacturer Part Number: M378T2953CZ3-CD5
• Manufacturer: Samsung Semiconductor

Specifications of M378T2953CZ3-CD5

• Lead Free Status / RoHS Status: Compliant

Note :
1. “Z” of Part number(11th digit) stand for Lead-free products.
2. “3” of Part number(12th digit) stand for Dummy Pad PCB products.
1.0 DDR2 Unbuffered DIMM Ordering Information
2.0 Features
3.0 Address Configuration
UDIMM
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
• Performance range
• JEDEC standard 1.8V ± 0.1V Power Supply
• V
• 200 MHz f
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than T
• Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16
• All of Lead-free products are compliant for RoHS
M378T3354CZ3-CE7/F7/E6/D5/CC
M378T3354CZ0-CE7/F7/E6/D5/CC
M378T6553CZ3-CE7/F7/E6/D5/CC
M378T6553CZ0-CE7/F7/E6/D5/CC
M378T2953CZ3-CE7/F7/E6/D5/CC
M378T2953CZ0-CE7/F7/E6/D5/CC
M391T6553CZ3-CE7/F7/E6/D5/CC
M391T6553CZ0-CE7/F7/E6/D5/CC
M391T2953CZ3-CE7/F7/E6/D5/CC
M391T2953CZ0-CE7/F7/E6/D5/CC
-
CL-tRCD-tRP
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
DDQ
support High Temperature Self-Refresh rate enable feature
32Mx16(512Mb) based Module
64Mx8(512Mb) based Module
= 1.8V ± 0.1V
Part Number
Organization
CK
for 400Mb/sec/pin, 267MHz f
E7 (DDR2-800)
5-5-5
400
533
800
-
Density
256MB
256MB
512MB
512MB
512MB
512MB
1GB
1GB
1GB
1GB
Row Address
F7 (DDR2-800)
CK
A0-A13
A0-A12
6-6-6
for 533Mb/sec/pin, 333MHz f
400
533
800
CASE
Organization
-
128Mx64
128Mx64
128Mx72
128Mx72
32Mx64
32Mx64
64Mx64
64Mx64
64Mx72
64Mx72
85°C, 3.9us at 85°C < T
x64 Non ECC
x72 ECC
4 of 24
E6 (DDR2-667)
Column Address
5-5-5
400
533
667
Component Composition
-
32Mx16(K4T51163QC)*4
32Mx16(K4T51163QC)*4
64Mx8(K4T51083QC)*16
64Mx8(K4T51083QC)*16
64Mx8(K4T51083QC)*18
64Mx8(K4T51083QC)*18
64Mx8(K4T51083QC)*8
64Mx8(K4T51083QC)*8
64Mx8(K4T51083QC)*9
64Mx8(K4T51083QC)*9
A0-A9
A0-A9
CK
CASE
for 667Mb/sec/pin, 400MHz f
D5 (DDR2-533)
< 95 °C
4-4-4
400
533
533
-
Bank Address
BA0-BA1
BA0-BA1
Number of Rank
Rev. 1.5 October 2006
CC (DDR2-400)
DDR2 SDRAM
3-3-3
400
400
1
1
1
1
2
2
1
1
2
2
-
-
CK
for 800Mb/sec/pin
Auto Precharge
A10
A10
Height
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
Mbps
Mbps
Mbps
Mbps
Unit
CK