RC28F640J3F75A NUMONYX, RC28F640J3F75A Datasheet - Page 44
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RC28F640J3F75A
Manufacturer Part Number
RC28F640J3F75A
Description
Manufacturer
NUMONYX
Datasheet
1.RC28F640J3F75A.pdf
(66 pages)
Specifications of RC28F640J3F75A
Lead Free Status / RoHS Status
Not Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
RC28F640J3F75A
Manufacturer:
TOSHIBA
Quantity:
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Part Number:
RC28F640J3F75A
Manufacturer:
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Quantity:
10 000
Table 29: Programming the 128-bit Protection Register Command Bus-Cycles
9.8.7
Table 30: Programming Protection Lock Register Command Bus-Cycles
Figure 15: 128-bit Protection Register Memory Map
Note:
Datasheet
44
Program OTP Register
Program OTP Register
A0 is not used in x16 mode when accessing the protection register map. See
A0 is used, see
Flowchart” on page
outside the defined PR address space will result in a Status Register error (SR.4 will be
set). Attempting to program a locked PR segment will result in a Status Register error
(SR.4 and SR.1 will be set).
Locking the 128-bit OTP Protection Register
The user-programmable segment of the PR is lockable by programming Bit 1 of the
Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to 0 at the
Numonyx factory to protect the unique device number. Bit 1 is set using the Protection
Program command to program “0xFFFD” to the PLR. After these bits have been
programmed, no further changes can be made to the values stored in the Protection
Register. Protection Program commands to a locked section will result in a Status
Register error (SR.4 and SR.1 will be set). The PR lockout state is not reversible.
Command
Command
Table 32
0x88
0x87
0x86
0x85
0x84
0x83
0x82
0x81
0x80
for x8 addressing.
Word Address
15 14 13 12 11 10 9
57. Any attempt to address Program OTP Register command
128-Bit Protection Register
Protection Lock Register
Numonyx
( Factory - Programmed )
( User - Programmable )
64- bit Segment
64- bit Segment
Device Address
Device Address
Address Bus
Address Bus
®
8
128-Mbit: A[23:1]
First Bus Cycle
First Bus Cycle
Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
64-Mbit: A[22:1]
32-Mbit: A[21:1]
7
6
5 4
3
2
Data Bus
Data Bus
1
00C0h
00C0h
0
Table 31
Register Offset
Address Bus
Address Bus
for x16 addressing. In x8 mode
80h
Second Bus Cycle
Second Bus Cycle
Register Data
Data Bus
Data Bus
FFFDh
March 2010
208032-02