RC28F640J3F75A NUMONYX, RC28F640J3F75A Datasheet - Page 10

• Manufacturer Part Number: RC28F640J3F75A
• Manufacturer: NUMONYX

Specifications of RC28F640J3F75A

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
10
The Status Register indicates when the WSM’s block erase, program, or lock-bit
configuration operation completes.
The STS (status) output gives an additional indicator of WSM activity by providing both
a hardware signal of status (versus software polling) and status masking (interrupt
masking for background block erase, for example). Status indication using STS
minimizes both CPU overhead and system power consumption. When configured in
level mode (default mode), it acts as a RY/BY# signal. When low, STS indicates that the
WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates
that the WSM is ready for a new command, block erase is suspended (and
programming is inactive), program is suspended, or the device is in reset/power-down
mode. Additionally, the configuration command allows the STS signal to be configured
to pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design
(see
decoder logic typically required for multi-chip designs. External logic is not required
when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module.
The BYTE# signal allows either x8 or x16 read/writes to the device:
Figure 1, “Memory Block Diagram for 32-, 64-, 128-Mbit” on page 11
block diagram.
When the device is disabled (see
Mb” on page
RP# is at V
consumption and provides write protection during reset. A reset time (t
required from RP# going high until data outputs are valid. Likewise, the device has a
wake time (t
V
IL
• BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high
• BYTE#-high enables16-bit operation; address A1 becomes the lowest order
, the WSM is reset and the Status Register is cleared.
byte.
address and address A0 is not used (don’t care).
Table 17, “Chip Enable Truth Table for 32-, 64-, 128-Mb” on page
IL
PHWL
, a further power-down mode is enabled which minimizes power
30), with CEx at V
) from RP#-high until writes to the CUI are recognized. With RP# at
Numonyx
IH
®
Table 17, “Chip Enable Truth Table for 32-, 64-, 128-
Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
and RP# at V
IH
, the standby mode is enabled. When
shows a device
30) reduces
PHQV
) is
March 2010
208032-02