CY7C4245V-25ASC Cypress Semiconductor Corp, CY7C4245V-25ASC Datasheet - Page 8

• Manufacturer Part Number: CY7C4245V-25ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4245V-25ASC

• Configuration: Dual
• Density: 64Kb
• Access Time (max): 15ns
• Word Size: 18b
• Organization: 4Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 30mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

Width Expansion Configuration
The CY7C42X5V can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode
all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full) flags
of every FIFO. This technique will avoid ready data from the FIFO that is “staggered” by one clock cycle due to the variations in skew
between RCLK and WCLK.
Depth Expansion Configuration (with Programmable Flags)
The CY7C42X5V can easily be adapted to applications requiring more than 64/256/512/1024/2048/4096 words of buffering.
shows Depth Expansion using three CY7C42X5Vs. Maximum depth is limited only by signal loading. Follow these steps:
Document #: 38-06029 Rev. *D
1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite
FULL FLAG (FF)
PAE and PAF flags are not precise.
PROGRAMMABLE(PAE)
DATA IN (D)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
Figure 2. Block Diagram of Low-Voltage Synchronous FIFO Memories Used in a Width Expansion Configuration
HALF FULL FLAG (HF)
LOAD (LD)
36
18
Figure
FF
demonstrates a 36-word width by using two CY7C42X5V.
RESET (RS)
7C4215V
7C4225V
7C4235V
7C4245V
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
EF
FIRST LOAD (FL)
18
18
FF
RESET (RS)
7C4215V
7C4225V
7C4235V
7C4245V
EF
18
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE(OE)
PROGRAMMABLE(PAF)
DATA OUT (Q)
CY7C4225V/4215V
CY7C4235V/4245V
EMPTYFLAG (EF)
36
Page 8 of 23
Figure
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