CY7C4245V-25ASC Cypress Semiconductor Corp, CY7C4245V-25ASC Datasheet - Page 5

• Manufacturer Part Number: CY7C4245V-25ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4245V-25ASC

• Configuration: Dual
• Density: 64Kb
• Access Time (max): 15ns
• Word Size: 18b
• Organization: 4Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 30mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

Pin Definitions
Document #: 38-06029 Rev. *D
D
Q
WEN
REN
WCLK
RCLK
WXO/HF
EF
FF
PAE
PAF
LD
FL/RT
WXI
RXI
RXO
RS
OE
V
Signal Name
CC
0−17
0−17
/SMODE
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
Read Clock
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
Write Expansion
Input
Read Expansion
Input
Read Expansion
Output
Reset
Output Enable
Synchronous
Almost Empty/
Almost Full Flags
Description
I/O
O Data outputs for an 18-bit bus.
O Dual-Mode Pin. Single device or width expansion - Half Full status flag. Cascaded –
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty
O When PAF is LOW, the FIFO is almost full based on the almost full offset
O Cascaded – Connected to RXI of next device.
I
I
I
I
I
I
I
I
I
I
I
I
Data inputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is
not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is
not Empty. When LD is asserted, RCLK reads data out of the programmable
flag-offset register.
Write Expansion Out signal, connected to WXI of next device.
offset value programmed into the FIFO. PAE is asynchronous when
V
to V
value programmed into the FIFO. PAF is asynchronous when V
tied to V
When LD is LOW, D
mable-flag-offset register.
Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to
V
expansion, FL is tied to V
function is also available in standalone mode by strobing RT.
Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to V
Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to V
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance)
state.
Dual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to V
Synchronous Almost Empty/Almost Full flags – tied to V
synchronized to RCLK, Almost Full synchronized to WCLK.)
CC
SS
; all other devices will have FL tied to V
SS
/SMODE is tied to V
.
CC
; it is synchronized to WCLK when V
0−17
CC
SS
(O
; it is synchronized to RCLK when V
on all devices. Not Cascaded – Tied to V
0−17
) are written (read) into (from) the program-
Function
CC
. In standard mode of width
CC
/SMODE is tied to V
CY7C4225V/4215V
CY7C4235V/4245V
SS
. (Almost Empty
CC
/SMODE is tied
CC
SS
/SMODE is
. Retransmit
SS
CC
.
.
Page 5 of 23
SS
SS
.
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