CY7C4245V-25ASC Cypress Semiconductor Corp, CY7C4245V-25ASC Datasheet - Page 6

• Manufacturer Part Number: CY7C4245V-25ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4245V-25ASC

• Configuration: Dual
• Density: 64Kb
• Access Time (max): 15ns
• Word Size: 18b
• Organization: 4Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 30mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

Architecture
The CY7C42X5V consists of an array of 64 to 4K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK, REN,
WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C42X5V
also includes the control signals WXI, RXI, WXO, RXO for depth
expansion.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. In order for the FIFO to reset to its
default state, a falling edge must occur on RS and the user must
not read or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the D
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory will be presented on the Q
will be presented on each rising edge of RCLK while REN is
active LOW and OE is LOW. REN must set up t
for it to be a valid read function. WEN must occur t
WCLK for it to be a valid write function.
An Output Enable (OE) pin is provided to three-state the Q
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q
after t
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
after additional reads occur.
Document #: 38-06029 Rev. *D
Note
1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
OE
. If devices are cascaded, the OE function will only
0−17
outputs. New data
ENS
0−17
before RCLK
outputs even
0−17
ENS
outputs
before
0–17
0-17
Programming
The CY7C42X5V devices contain two 12-bit offset registers.
Data present on D
distance from Empty (Full) that the Almost Empty (Almost Full)
flags become active. If the user elects not to program the FIFO’s
flags, the default offset values are used (see
Load LD pin is set LOW and WEN is set LOW, data on the inputs
D
LOW-to-HIGH transition of the write clock (WCLK). When the LD
pin and WEN are held LOW then data is written into the Full offset
register on the second LOW-to-HIGH transition of the Write
Clock (WCLK). The third transition of the Write Clock (WCLK)
again writes to the Empty offset register (see
offset registers does not have to occur at one time. One or two
offset registers can be written and then, by bringing the LD pin
HIGH, the FIFO is returned to normal read/write operation. When
the LD pin is set LOW, and WEN is LOW, the next offset register
in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Table 1. Write Offset Register
LD WEN
0–11
0
0
1
1
is written into the Empty offset register on the first
0
1
0
1
WCLK
0–11
[1]
during a program write will determine the
Writing to offset registers:
Empty Offset
Full Offset
No Operation
Write Into FIFO
No Operation
CY7C4225V/4215V
CY7C4235V/4245V
Selection
Table
Table
2). When the
1). Writing all
Page 6 of 23
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