CY7C4245V-25ASC Cypress Semiconductor Corp, CY7C4245V-25ASC Datasheet - Page 13

CY7C4245V-25ASC

Manufacturer Part Number
CY7C4245V-25ASC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C4245V-25ASC

Configuration
Dual
Density
64Kb
Access Time (max)
15ns
Word Size
18b
Organization
4Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
40MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
30mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Not Compliant
Switching Waveforms
Notes
Document #: 38-06029 Rev. *D
15. t
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
REN, WEN,
Q
0
EF,PAE
FF,PAF,
Q
WCLK
RCLK
–Q
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
WEN
REN
0
–Q
OE
EF
17
RS
HF
LD
17
t
ENS
t
OLZ
(continued)
t
ENH
t
CLKH
t
t
A
REF
t
t
t
RSF
RSF
RSF
t
OE
t
RS
Figure 6. Read Cycle Timing
t
Figure 7. Reset Timing
CLK
t
SKEW2
NO OPERATION
SKEW2
[15]
t
CLKL
, then EF may not change state until the next RCLK edge.
[16]
VALID DATA
t
RSR
t
REF
t
OHZ
CY7C4225V/4215V
CY7C4235V/4245V
OE = 1
OE = 0
[17]
Page 13 of 23
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