K4S641632KUC75 Samsung Semiconductor, K4S641632KUC75 Datasheet - Page 10

• Manufacturer Part Number: K4S641632KUC75
• Manufacturer: Samsung Semiconductor

Specifications of K4S641632KUC75

• Lead Free Status / RoHS Status: Compliant

AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
K4S640832K
K4S641632K
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Output
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
6. t
(Fig. 1) DC output load circuit
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
and then rounding off to the next higher integer.
RC
870Ω
=t
Parameter
RFC,
Parameter
t
RDL
= t
WR
.
3.3V
CAS latency = 3
CAS latency = 2
1200Ω
30pF
V
V
t
t
t
t
t
t
t
t
t
OH
OL
RAS
RRD
RCD
t
t
CCD
Symbol
RAS
RDL
DAL
CDL
BDL
RC
RP
(DC) = 0.4V, I
(DC) = 2.4V, I
(V
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
DD
= 3.3V ± 0.3V, T
10 of 14
OL
OH
50
10
15
15
40
55
= 2mA
= -2mA
A
2 CLK + tRP
= 0 to 70°C)
Version
See Fig. 2
tr/tf = 1/1
2.4/0.4
100
Value
60
12
18
18
42
60
2
1
1
1
2
1
1.4
1.4
Output
(Fig. 2) AC output load circuit
75
15
20
20
45
65
Rev. 1.1 February 2006
Synchronous DRAM
Z0 = 50Ω
Unit
CLK
CLK
CLK
CLK
ea
ns
ns
ns
ns
us
ns
-
Vtt = 1.4V
Unit
50Ω
ns
30pF
V
V
V
Note
2,5,6
1, 6
1
1
1
1
5
2
2
3
4