MT48LC16M16A2P-75:D Micron Technology Inc, MT48LC16M16A2P-75:D Datasheet - Page 34

• Manufacturer Part Number: MT48LC16M16A2P-75:D
• Description: IC, SDRAM, 256MBIT, 133MHZ, TSOP-54
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC16M16A2P-75:D

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Type: DRAM - Sychronous
• Memory Configuration: 16 X 16
• Access Time: 5.4ns
• Page Size: 256Mbit
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Format - Memory: RAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP (0.400", 10.16mm Width)
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

READ
Figure 14: READ Command
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
The READ command is used to initiate a burst read access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided selects the starting
column location. The value on input A10 determines whether auto precharge is used. If
auto precharge is selected, the row being accessed is precharged at the end of the READ
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Read data appears on the DQ subject to the logic level on the DQM inputs two clocks
earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-
Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data.
BA0, BA1
Address
1. EN AP = enable auto precharge, DIS AP = disable auto precharge.
RAS#
CAS#
A10
WE#
CKE
CLK
CS#
1
HIGH
Column address
Bank address
DIS AP
EN AP
34
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 SDRAM
© 1999 Micron Technology, Inc. All rights reserved.
Commands