RD38F2040W0YBQ0 SB93 Micron Technology Inc, RD38F2040W0YBQ0 SB93 Datasheet - Page 40

• Manufacturer Part Number: RD38F2040W0YBQ0 SB93
• Manufacturer: Micron Technology Inc

Specifications of RD38F2040W0YBQ0 SB93

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Warning:
9.3.1.2
9.3.1.3
Table 16: Optional PSRAM BCR Latency Counter Settings in Variable Latency
Table 17: Optional PSRAM BCR Latency Counter Settings in Fixed Latency
Datasheet
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When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
PSRAM Initial Latency BCR Bit
The PSRAM latency is related to the number of clock cycles from the burst-init
command to be either 1
write.)
The minimum latency in Variable Latency mode is defined by the Latency Counter
setting in the BCR. Additional WAIT cycles may be added in Variable Latency mode if
the burst-init Read command collides with an on-going internal refresh. Additional
WAIT cycles are not added for burst-init Write commands in Variable Latency mode.
PSRAM Latency Counter BCR Bit
The latency counter defines the number of clock cycles that pass before the first output
data is valid (read burst) or before the first input data is valid (read burst.) Each
Latency Code setting has an associate maximum PSRAM clock frequency. In the case of
Variable Latency the first access delay might be extended by additional wait cycles in
case the burst read access collides with an ongoing self-refresh operation. The allowed
values of the Latency Counter also depend on the Initial Latency setting in BCR.
• In Fixed Latency mode, the number of clock cycles from bust-init command to valid
• In Variable Latency mode, the number of clock cycles from bust-init command to
Latency
Counter
Latency
Counter
data is always fixed as defined by the Latency Counter setting in the BCR.
valid data output (read burst) is variable depending on internal device operation.
Others
Others
010
011
010
011
100
101
110
Code 2; Max 33 MHz
Code 3; Max 52 MHz
Code 4; Max 66 MHz
Code 5; Max 75 Mhz
Code 6; Max 104 MHz
Reserved
Code 2; Max 66 MHz
Code 3; Max 80 MHz
Reserved
st
PSRAM
PSRAM
valid data output (read burst) or 1
128-Mbit W18 Family with Synchronous PSRAM
st
valid data input (burst
Order Number: 311760-10
November 2007