RD38F2040W0YBQ0 SB93 Micron Technology Inc, RD38F2040W0YBQ0 SB93 Datasheet - Page 36

• Manufacturer Part Number: RD38F2040W0YBQ0 SB93
• Manufacturer: Micron Technology Inc

Specifications of RD38F2040W0YBQ0 SB93

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 23: PSRAM WAIT Behavior during Burst Write End-of-Row with Wrap Off
Figure 24: PSRAM WAIT Behavior during Burst Read End-of-Row with Wrap Off
Datasheet
36
DQ[15:0]
DQ[15:0]
WAIT
CLK
CE#
During variable latency burst write operations and fixed latency burst write and read
operations the initial latency is fixed so the system is not required to monitor the WAIT
signal although the WAIT signal is fully functional and may be monitored by the
system. The system should terminate or interrupt the burst access to avoid row
boundary crossings in both fixed and variable latency mode.
To match with the Flash interfaces of different microprocessor types the polarity and
the timing of the WAIT signal can be configured. The polarity can be programmed to be
either active low or active high. The timing of the WAIT signal can be adjusted as well.
Depending on the BCR setting the WAIT signal will be either asserted at the same time
the data becomes invalid or it will be set active one clock period in advance.
In asynchronous mode including page mode, the WAIT signal is not used but stays
asserted as BCR bit 10 is specified. In this case, the system should ignore the WAIT
signal. When the PSRAM is deselected or in deep power down, the WAIT output will be
in a high impedance state.
WAIT
CLK
CE#
End of Row
End of Row
tWK
A
tWK
tHD
tHD
tCSS
tWZ
tWK
tCSS
B
tWZ
tOD
128-Mbit W18 Family with Synchronous PSRAM
Order Number: 311760-10
November 2007