RD38F2040W0YBQ0 SB93 Micron Technology Inc, RD38F2040W0YBQ0 SB93 Datasheet - Page 35

• Manufacturer Part Number: RD38F2040W0YBQ0 SB93
• Manufacturer: Micron Technology Inc

Specifications of RD38F2040W0YBQ0 SB93

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

128-Mbit W18 Family with Synchronous PSRAM
Warning:
8.4
8.5
8.6
November 2007
Order Number: 311760-10
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
PSRAM Deselect
The Deselect function prevents new commands from being executed by the PSRAM. A
deselected PSRAM places its I/O signals in a high impedance state. To place the device
in a deselected state:
PSRAM Deep Power Down
Deep Power Down (DPD) stops all refresh-related activities and the current
consumption of the device drops to a very low level. The contents of the Memory are
not preserved. After setting RCR4 = 1b, to place the device in the DPD state
PSRAM WAIT Signal
The WAIT signal is used in synchronous mode to indicate to the host system periods of
invalid data. Periods of invalid data are caused by:
For fixed length bursts with wrap on, WAIT remains deasserted when the End of Row is
reached and the burst will wrap around and continue without any delay. Therefore for
fixed length bursts with wrap on, WAIT is only asserted during First access delays.
For continuous or wrap-off burst length configuration, End of Row condition, WAIT will
transition from being de-asserted to being asserted within the time window defined by
tKOH and tWK. Depending on the implementation for a burst write, WAIT may be
asserted at the same time as the delay (condition A of
later (condition B of
1. First access delays, or
2. End of Row condition for continuous or wrap-off burst settings.
• In Synchronous mode, ADV# deasserted hold time (tHD) must be observed.
• CE# must be deasserted.
• CLK must be held in a static low state while in Asynchronous mode. CLK may toggle
• CE# must be deasserted.
• CLK must be held in a static low state to achieve minimum current consumption
during a NOP in Synchronous mode.
levels.
Figure
23.) This inconsistency does not occur during burst read.
Figure
23) or one clock cycle
Datasheet
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