S71PL129JB0BAW9Z0 Spansion Inc., S71PL129JB0BAW9Z0 Datasheet - Page 21

• Manufacturer Part Number: S71PL129JB0BAW9Z0
• Manufacturer: Spansion Inc.

Specifications of S71PL129JB0BAW9Z0

• Lead Free Status / RoHS Status: Compliant

Device Bus Operations
Legend: L = Logic Low = V
Address, A
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
2. WP#/ACC must be high when writing to upper two and lower two sectors.
October 28, 2005 S71PL129Jxx_00_A8
Read
Write
Standby
Output Disable
Reset
Temporary Sector Unprotect
(High Voltage)
““High Voltage Sector Protection”
Requirements for Reading Array Data
IN
Operation
= Address In, D
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device.
quired, and the resulting output. The following subsections describe each of these
operations in further detail.
To read array data from the outputs, the system must drive the OE# and appro-
priate CE# pins to V
select the lower (CE1#) or upper (CE2#) halves of the device. CE# is the power
control. OE# is the output control and gates array data to the output pins. WE#
should remain at V
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
See
in the DC Characteristics table represents the active current specification for
reading array data.
Table 24
Table 1
IL
A d v a n c e
, H = Logic High = V
IN
for timing specifications and
= Data In, D
lists the device bus operations, the inputs and control levels re-
0.3 V
CE1#
V
H
H
IO
L
L
L
X
X
IH
Table 1. PL129J Device Bus Operations
on page 37.”
±
.
IL
. In PL129J, CE1# and CE2# are the power control and
S71PL129JC0/S71PL129JB0/S71PL129JA0
0.3 V
CE2#
V
OUT
IO
H
H
X
X
L
L
L
I n f o r m a t i o n
±
= Data Out
IH
, V
OE#
ID
H
H
X
X
X
L
= 11.5–12.5 V, V
Figure 11
WE#
H
X
H
X
X
L
RESET#
0.3 V
V
for the timing diagram. I
V
IO
H
H
H
L
HH
ID
±
= 8.5–9.5 V, X = Don’t Care, SA = Sector
WP#/ACC
(Note
X
X
X
X
X
X
2)
Addresses
(A21–A0)
A
A
A
CC1
X
X
X
IN
IN
IN
High-Z
High-Z
High-Z
DQ15–
D
DQ0
D
D
OUT
IN
IN
19