S71PL129JB0BAW9Z0 Spansion Inc., S71PL129JB0BAW9Z0 Datasheet
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S71PL129JB0BAW9Z0 Summary of contents
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S71PL129JC0/S71PL129JB0/S71PL129JA0 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM 128 Megabit (8M x 16-bit) CMOS 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory with 64/32/16 Megabit (4M/2M/1M x 16-bit) Pseudo-Static RAM Data Sheet Notice to Readers: The Advance Information status ...
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Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, in- cluding development, qualification, initial production, and full production. In ...
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S71PL129JC0/S71PL129JB0/S71PL129JA0 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM 128 Megabit (8M x 16-bit) CMOS 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory with 64/32/16 Megabit (4M/2M/1M x 16-bit) Pseudo-Static RAM Data Sheet Distinctive Characteristics MCP Features Power supply voltage ...
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Product Selector Guide 128 Mb Flash Memory Device-Model# pSRAM density S71PL129JA0-9P 16M pSRAM S71PL129JB0-9Z 32M pSRAM S71PL129JB0-9B 32M pSRAM S71PL129JB0-9U 32M pSRAM S71PL129JC0-9B 64M pSRAM S71PL129JC0-9Z 64M pSRAM S71PL129JC0-9U 64M pSRAM ...
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S71PL129JC0/S71PL129JB0/S71PL129JA0 Notice On Data Sheet Designations . . . . . . . . . . . ii Advance Information .......................................................................................ii Preliminary ..........................................................................................................ii Combination .......................................................................................................ii Full Production (No Designation on Document) ...................................ii S71PL129JC0/S71PL129JB0/S71PL129JA0 ...
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RY/BY#: Ready/Busy# .......................................................................................58 DQ6: Toggle Bit I ............................................................................................... 58 Figure 7. Toggle Bit Algorithm.............................................. 60 DQ2: Toggle Bit II .............................................................................................. 60 Reading Toggle Bits DQ6/DQ2 ..................................................................... 60 DQ5: Exceeded Timing Limits ........................................................................ 61 DQ3: Sector Erase Timer ................................................................................. 61 Table ...
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Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 121 Power Up ............................................................................................................. 121 Figure ...
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MCP Block Diagram CE1#f CE2#f WP#/ACC RESET# Flash-only Address Shared Address OE# WE# CE#s UB#s LB#s CE2#ps CEM1# ...
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Connection Diagram VSS H2 H3 CE1#f OE CE1#s DQ0 K3 DQ8 M1 ...
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Input/Output Description Pin Description A21–A0 DQ15–DQ0 CE1#f CE2#f CE1#ps CE2ps OE# WE# RY/BY# UB# LB# RESET# WP#/ACC Logic Symbol ...
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Ordering Information The order number is formed by a valid combinations of the following: S71PL 129 October 28, 2005 S71PL129Jxx_00_A8 ...
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S71PL129J Valid Combinations Base Ordering Package & Part Number Temperature S71PL129JA0 S71PL129JB0 S71PL129JB0 S71PL129JB0 BAW S71PL129JC0 S71PL129JC0 S71PL129JC0 S71PL129JA0 S71PL129JB0 S71PL129JB0 S71PL129JB0 BFW S71PL129JC0 S71PL129JC0 S71PL129JC0 Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package ...
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Physical Dimensions TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA 11.6 mm Package D 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b 64X ...
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S29PL129J for MCP 128 Megabit ( 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Datasheet Distinctive Characteristics Architectural Advantages 128 Mbit Page Mode devices — Page size of 8 words: Fast page read access from ...
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Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and ...
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General Description The PL129J is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device can be pro- grammed in-system or in standard EPROM ...
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write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the ...
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Block Diagram RY/BY# (See Note RESET# WE# State Control Command Register CE# OE# V Detector CC Amax–A3 A2–A0 Notes: 1. RY/BY open drain output. 2. For PL129J there are two CE# (CE1# and CE2#) ...
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Simultaneous Read/Write Block Diagram (PL129J Mux A21–A0 RY/BY# A21–A0 RESET# STATE WE# CONTROL CE1# & CE2# COMMAND REGISTER WP#/ACC DQ0–DQ15 A21–A0 Mux Notes: 1. Amax = A21 (PL129J) October ...
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Pin Description Amax–A0 DQ15–DQ0 CE# OE# WE RY/BY# WP#/ACC RESET# CE1#, CE2# Notes: 1. Amax = A21 Logic Symbol ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory ...
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Random Read (Non-Page Read) Address access time (t output data. The chip enable access time (t dresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of ...
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Bank 2A Bank 2B Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE1# ...
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The device enters the CMOS standby mode when the CE1# or CE#2 and RESET# pins are both held at V range than CE1# or CE#2 and RESET# are held ± 0.3 V, the device ...
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Table 3. S29PL129J Sector Architecture (Sheet Bank Sector CE1# SA1-0 SA1-1 SA1-2 SA1-3 SA1-4 SA1-5 SA1-6 SA1-7 SA1-8 SA1-9 SA1-10 SA1-11 SA1-12 SA1-13 SA1-14 SA1-15 SA1-16 SA1-17 SA1-18 SA1-19 SA1-20 ...
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Table 3. S29PL129J Sector Architecture (Sheet Bank Sector CE1# SA1-39 SA1-40 SA1-41 SA1-42 SA1-43 SA1-44 SA1-45 SA1-46 SA1-47 SA1-48 SA1-49 SA1-50 SA1-51 SA1-52 SA1-53 SA1-54 SA1-55 SA1-56 SA1-57 SA1-58 SA1-59 SA1-60 SA1-61 SA1-62 SA1-63 SA1-64 SA1-65 SA1-66 ...
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Table 3. S29PL129J Sector Architecture (Sheet Bank Sector CE1# SA1-83 SA1-84 SA1-85 SA1-86 SA1-87 SA1-88 SA1-89 SA1-90 SA1-91 SA1-92 SA1-93 SA1-94 SA1-95 SA1-96 SA1-97 SA1-98 SA1-99 SA1-100 SA1-101 SA1-102 SA1-103 ...
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Table 3. S29PL129J Sector Architecture (Sheet Bank Sector CE1# SA1-127 SA1-128 SA1-129 SA1-130 SA1-131 SA1-132 SA1-133 SA1-134 SA2-0 SA2-1 SA2-2 SA2-3 SA2-4 SA2-5 SA2-6 SA2-7 SA2-8 SA2-9 SA2-10 SA2-11 SA2-12 SA2-13 SA2-14 SA2-15 SA2-16 SA2-17 SA2-18 SA2-19 ...
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Table 3. S29PL129J Sector Architecture (Sheet Bank Sector CE1# SA2-36 SA2-37 SA2-38 SA2-39 SA2-40 SA2-41 SA2-42 SA2-43 SA2-44 SA2-45 SA2-46 SA2-47 SA2-48 SA2-49 SA2-50 SA2-51 SA2-52 SA2-53 SA2-54 SA2-55 SA2-56 ...
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Table 3. S29PL129J Sector Architecture (Sheet Bank Sector CE1# SA2-80 SA2-81 SA2-82 SA2-83 SA2-84 SA2-85 SA2-86 SA2-87 SA2-88 SA2-89 SA2-90 SA2-91 SA2-92 SA2-93 SA2-94 SA2-95 SA2-96 SA2-97 SA2-98 SA2-99 SA2-100 SA2-101 SA2-102 SA2-103 SA2-104 SA2-105 SA2-106 SA2-107 ...
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Table 3. S29PL129J Sector Architecture (Sheet Bank Sector CE1# SA2-124 SA2-125 SA2-126 SA2-127 SA2-128 SA2-129 SA2-130 SA2-131 SA2-132 SA2-133 SA2-134 Table 4. Secured Silicon Sector Addresses Factory-Locked Area Customer-Lockable Area ...
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Description CE1# CE2# OE# Manufacturer L H ID: Spansion products L H Read Cycle Read L Cycle Read Cycle Sector L H Protection L ...
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Table 6. PL129J Boot Sector/Sector Block Addresses for Protection/Unprotection CE1# Control Sector Group A21-12 SA1-0 0000000000 SA1-1 0000000001 SA1-2 0000000010 SA1-3 0000000011 SA1-4 0000000100 SA1-5 0000000101 SA1-6 0000000110 SA1-7 0000000111 SA1-8 0000001XXX SA1-9 ...
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Selecting a Sector Protection Mode The device is shipped with all sectors unprotected. Optional Spansion program- ming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details ...
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programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Per- sistent Sector Protection Mode into the Password Protection ...
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PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs are set ...
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summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. ...
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Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ...
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Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit ...
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START PLSCNT = 1 RESET Wait 4 μs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Wait 100 µs ...
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Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin grammed or erased ...
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Factory-Locked Area (64 words) The factory-locked area of the Secured Silicon Sector (000000h-00003Fh) is locked when the part is shipped, whether or not the area was programmed at the factory. The Secured Silicon Sector Factory-locked Indicator Bit (DQ7) is perma- ...
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Figure 3. Secured Silicon Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data ...
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Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. Software support can then be device-independent, ...
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Addresses Data 1Bh 0027h 1Ch 0036h 1Dh 0000h 1Eh 0000h 1Fh 0003h 20h 0000h 21h 0009h 22h 0000h 23h 0004h 24h 0000h 25h 0004h 26h 0000h Addresses Data 27h 0018h (PL129J) 28h 0001h ...
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Table 11. Primary Vendor-Specific Extended Query (Sheet Addresses Data 43h 0031h 44h 0033h 45h TBD 46h 0002h 47h 0001h 48h 0001h 49h 0007h (PLxxxJ) 4Ah 00E7h (PL129J) 4Bh 0000h 4Ch 0002h (PLxxxJ) 4Dh 0085h 4Eh 0095h 4Fh ...
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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. sequences. Writing incorrect address and data values or writing them in the improper sequence may place ...
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If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the ...
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Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank ...
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Increment Address Note: See Table 12 Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is ini- tiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write ...
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Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two addi- tional unlock ...
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Notes: 1. See Table 12 for erase command sequence. 2. See “DQ3: Sector Erase Timer” timer. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or ...
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operation using the DQ7 or DQ6 status bits, just as in the standard Word Program operation. See “Write Operation Status” In the erase-suspend-read mode, the system can also issue the autoselect com- mand ...
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Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting ...
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correctly match a password. If the command is issued before the 2 tion window for each portion of the unlock, the command will be ignored. Once the Password Unlock command is entered, ...
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DYB protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. Command The programming ...
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During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than ...
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PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for ...
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During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete the bank enters the Erase Suspend mode, Data# Polling produces a “1” ...
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Notes Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be ...
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During an Embedded Program or Erase algorithm operation, successive read cy- cles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When ...
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Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See gle Bit II” for more information. DQ2: Toggle Bit II The “Toggle Bit II” ...
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store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . ...
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Operating Ranges Operating ranges define those limits between which the functionality of the de- vice is guaranteed. Industrial (I) Devices Ambient Temperature (T Extended (E) Devices Ambient Temperature (T Supply Voltages ...
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Characteristics Parameter Parameter Description Symbol I Input Load Current LI I A9, OE#, RESET# Input Load Current LIT I Reset Leakage Current LR I Output Leakage Current Active Read ...
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AC Characteristics Test Conditions Device Under Test Note: Diodes are IN3064 or equivalent Output Load Output Load Capacitance, C (including jig capacitance) L Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference ...
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VIO VIO/2 In 0.0 V Figure 10. Input Waveforms and Measurement Levels VCC RampRate All DC characteristics are specified for a V >=V - 100 mV. If the V CCQ required.+ Read Operations ...
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Addresses CE# OE# WE# Data RESET# RY/BY Notes: 1. S29PL129J - During CE1# transitions, CE2 S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2# Amax-A3 A2-A0 Data ...
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Reset Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# ...
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Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time AVAV Address Setup Time AVWL AS Address Setup Time to OE# low during toggle bit t ASO polling t t Address Hold Time WLAX AH Address ...
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Timing Diagrams Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data, ...
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Erase Command Sequence (last two cycles Addresses 2AAh CE# OE# WE Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address for reading status data (see page ...
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Valid PA Addresses CE# OE WE# t WPH t DS Valid Data In WE# Controlled Write Cycle Figure 17. Back-to-back Read/Write Cycle Timings Addresses t ...
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Addresses CE# t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Notes Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle ...
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Protect/Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary Sector t RSP ...
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RESET# SA, A6, A1, A0 Sector Group Protect/Unprotect Data 60h 1 µs CE# WE# OE# Notes: 1. For sector protect For sector unprotect ...
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Controlled Erase Operations Table 22. Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time AVAV Address Setup Time AVWL Address ...
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Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation program address, ...
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CE1# CE2# Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control Table 25. Erase And Programming Performance Parameter Sector Erase Time Chip Erase Time PL129J Word Program Time Accelerated Word Program ...
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Type 6 2M Word by 16-bit CMOS Pseudo Static RAM (32M) 4M Word by 16-bit CMOS Pseudo Static RAM (64M ) Features Single power supply voltage of 2.6 to 3.3 V Direct TTL compatibility for all inputs and outputs ...
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Functional Description Mode CE1# CE2 Read (Word) L Read (Lower Byte) L Read (Upper Byte) L Write (Word) L Write (Lower Byte) L Write (Upper Byte) L Outputs Disabled L Standby H Deep ...
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DC Characteristics (Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note Symbol Parameter Input Leakage Current Output Leakage I Output disable Current V Output High Voltage I ...
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Symbol t Output Data Hold Time OH t Page Mode Time PM t Page Mode Cycle Time PC t Page Mode Address Access Time AA t Page Mode Output Data Hold Time AOH ...
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Timing Diagrams Read Timings Address A0 to A20(32M A21(64M) CE1# CE2 OE# WE# UB# , LB# D OUT Hi-Z I/O1 to I/O16 ...
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Address Address A3 to A20(32M A21(64M) CE1# CE2 OE# WE# UB#, LB# D OUT Hi-Z I/O1 to I/O16 Figure 25. Page Read Cycle (8 Words Access) October 28, ...
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Write Timings Address A0 to A20 (32M A21(64M) WE# CE1 CE2 UB# , LB# D OUT I/O1 to I/O16 D IN I/O1 to I/O16 Figure 26. Write Cycle #1 (WE# Controlled) (See Note ...
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Address A0 to A20 (32M A21(64M) WE# CE1 CE2 UB#, LB# D OUT I/O1 to I/O16 D IN I/O1 to I/O16 Figure 27. Write Cycle #2 (CE# Controlled) (See ...
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Provisions of Address Skew Read In case multiple invalid address cycles shorter than active status, at least one valid address cycle over t ing 10µs. CE1# WE# Address Write In case multiple invalid address cycles shorter than ...
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Type 1 4Mbit (256K Word x 16-bit) 8Mbit (512K Word x 16-bit) 16Mbit (1M Word x 16-bit) 32Mbit (2M Word x 16-bit) 64Mbit (4M Word x 16-bit) Functional Description Mode CE# CE2/ZZ# Read (word Read (lower byte) ...
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DC Characteristics (4Mb pSRAM Asynchronous) Symbol Parameter V Power Supply CC V Input High Level IH V Input Low Level IL Input Leakage I IL Current Output Leakage I LO Current Output High V OH Voltage Output Low V OL ...
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Characteristics (8Mb pSRAM Asynchronous) Version Performance Grade Density Symbol Parameter Conditions V Power Supply CC V Input High Level IH V Input Low Level IL Input Leakage I Vin = 0 to ...
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DC Characteristics (16Mb pSRAM Asynchronous) Symbol Parameter V Power Supply CC V Input High Level IH V Input Low Level IL I Input Leakage Current IL I Output Leakage Current LO V Output High Voltage OH V Output Low Voltage ...
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Characteristics (16Mb pSRAM Page Mode) Performance Grade Density Symbol Parameter Conditions V Power Supply CC Input High V IH Level Input Low V IL Level Input Leakage I Vin = 0 to ...
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DC Characteristics (32Mb pSRAM Page Mode) Version Performance Grade Density Symbol Parameter Conditions Power V CC Supply Input High V IH Level Input Low V IL Level Input I Leakage Vin = Current Output OE ...
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Characteristics (64Mb pSRAM Page Mode) Symbol Parameter V Power Supply CC V Input High Level IH V Input Low Level IL Input Leakage I IL Current Output Leakage I LO Current Output ...
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Output Load Circuit Power Up Sequence After applying power, maintain a stable power supply for a minimum of 200 µs after CE# > ...
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Characteristics (4Mb pSRAM Page Mode) 3 Volt October 28, 2005 S71PL129Jxx_00_A8 Asynchronous Performance Grade -70 Density 4Mb pSRAM Symbol Parameter Min ...
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Volt Asynchronous Performance Grade -70 Density 4Mb pSRAM Symbol Parameter Min Max twc Write cycle time 70 Chipselect to end ...
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Characteristics (8Mb pSRAM Asynchronous) Version Performance Grade Density 3 Volt Symbol Parameter trc Read cycle time Address Access taa Time Chip select to tco output Output enable to toe valid output UB#, ...
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Version Performance Grade Density 3 Volt Symbol Parameter twc Write cycle time Chip select to tcw end of write Address set up tas Time Address valid to taw end of write UB#, LB# valid tbw to end of write twp ...
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Characteristics (16Mb pSRAM Asynchronous) Performance Grade 3 Volt Symbol trc taa tco toe tba tlz tblz tolz thz tbhz tohz toh October 28, 2005 S71PL129Jxx_00_A8 ...
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Performance Grade 3 Volt Symbol twc tcw tas taw tbw twp twr twhz tdw tdh tow tow tpc tpa twpc tcp 102 ...
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Characteristics (16Mb pSRAM Page Mode) Performance Grade Density 3 Volt Symbol Parameter trc Read cycle time Address Access taa Time Chip select to tco output Output enable to toe valid output UB#, ...
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Performance Grade Density 3 Volt Symbol Parameter twc Write cycle time Chipselect to end tcw of write Address set up tas Time Address valid to taw end of write UB#, LB# valid tbw to end of write twp Write pulse ...
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Characteristics (32Mb pSRAM Page Mode) Version Performance Grade Density 3 Volt Symbol Parameter trc Read cycle time Address Access taa Time Chip select to tco output Output enable to toe valid output ...
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Version Performance Grade Density 3 Volt Symbol Parameter twc Write cycle time Chipselect to end tcw of write Address set up tas Time Address valid to taw end of write UB#, LB# valid tbw to end of write twp Write ...
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Characteristics (64Mb pSRAM Page Mode) 3 Volt October 28, 2005 S71PL129Jxx_00_A8 Page Mode Performance Grade -70 Density 64Mb pSRAM Symbol Parameter ...
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Volt Timing Diagrams Read Cycle Address Previous Data Valid Data Out Figure 33. Timing of Read Cycle (CE 108 ...
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Address CE# OE# LB#, UB# High-Z Data Out Figure 34. Timing Waveform of Read Cycle (WE October 28, 2005 S71PL129Jxx_00_A8 ...
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Page Address (A4 - A20) Word Address (A0 - A3) CE# OE# LB#, UB# High-Z Data Out Figure 35. Timing Waveform of Page Mode Read Cycle (WE 110 ...
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Write Cycle Addr es s CE# LB#, UB# WE# High-Z Dat Out Figure 36. Timing Waveform of Write Cycle (WE# Control, ZZ dres s CE# LB#, ...
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Page A ddr 20) Wor d A ddr CE# WE# LB#, UB# High-Z Dat a Out Figure 38. Timing Waveform of Page Mode Write Cycle (ZZ# = ...
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freshed. The data in the remainder of the array will be lost. The PASR operation mode is only available during standby time (ZZ# low) and once ZZ# is returned high, the device resumes ...
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A21 - A8 A7 Reserved Must set to all 0 Page Mode 0 = Page Mode Disabled (default Page Mode Enabled Address CE# WE# t CDZZ ZZ# Figure 40. Mode Register Update Timings (UB#, LB#, OE# are Don’t ...
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ZZ# t CDZZ CE# Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M CE# WE# LB#, UB# t ZZWE ZZ# Figure 42. Deep Sleep Mode - Entry/Exit Timings (for ...
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Address Patterns for PASR (A4=1) (64M Active Section Top quarter of die Top half of die Reserved PASR Bottom quarter of ...
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Deep ICC Characteristics (for 64Mb) Item Symbol PASR Mode Standby Current I PASR Item Temperature Compensated Refresh Current Item Symbol Deep Sleep Current I ZZ Address Patterns for PAR (A3= 0, A4=1) (32M) ...
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Low Power ICC Characteristics (32M) Item Symbol PAR Mode Standby Current I PAR RMS Mode Standby Current I RMSSB Deep Sleep Current I ZZ Address Patterns for PAR (A3= 0, A4=1) (16M Active Section ...
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Type 2 pSRAM 16Mbit (1M Word x 16-bit) 32Mbit (2M Word x 16-bit) 64Mbit (4M Word x 16-bit) 128Mbit (8M Word x 16-bit) Features Process Technology: CMOS Organization: x16 bit Power Supply Voltage: 2.7~3.1V Product Information Density V 16Mb 2.7-3.1V ...
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Pin Description Pin Name CS1#, CS2 OE# WE# LB#, UB# A0-A19 (16M) A0-A20 (32M) A0-A21 (64M) A0-A22 (128M) I/O0-I/O15 CCQ SSQ NC DNU Power Up Sequence 1. Apply power. 2. Maintain stable power (V ...
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Timing Diagrams Power Up V CC(Min CS2 Notes: 1. After V reaches V (Min.), wait 200 µs with CS1# high. Then the device gets into the normal operation ...
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Legend:X = Don’t care (must be low or high state). Absolute Maximum Ratings Item Voltage on any pin relative to V Voltage on V supply relative Power Dissipation Operating Temperature Notes: 1. Stresses greater than those listed ...
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and Operating Characteristics Common Item Symbol Input Leakage Current I LI Output Leakage Current I LO Output Low Voltage V OL Output High Voltage V OH October 28, 2005 S71PL129Jxx_00_A8 I n ...
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Item Symbol Average Operating Current I CC2 Standby Current (CMOS) I SB1 Notes: 1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the ...
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64M pSRAM Item Symbol I Average Operating Current I CC2 Standby Current (CMOS) I SB1 Notes: 1. Standby mode is supposed to be set up after at least one active operation after power ...
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AC Operating Conditions Test Conditions (Test Load and Test Input/Output Reference) Input pulse level: 0 2.2 V (16Mb, 32Mb, 128Mb); 0 2.2 V (64Mb) Input rising and falling time: 5ns (16Mb, 32Mb); 3ns (64Mb, 128Mb) Input ...
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Characteristics (Ta = -40°C to 85°C, V Symbol t Read Cycle Time RC t Address Access Time AA t Chip Select to Output CO t Output Enable to Valid Output OE t ...
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Timing Diagrams Read Timings Address Data Out Previous Data Valid Figure 46. Timing Waveform of Read Cycle(1) Notes: 1. Address Controlled, CS1#=OE#=V Address CS1# CS2 UB#, LB# OE# Data out High-Z Figure 47. Timing Waveform of Read Cycle(2) Notes: 1. ...
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Address A1~A0 CS1# CS2 OE# DQ15~DQ0 Figure 48. Timing Waveform of Page Cycle (Page Mode Only) Notes: 1. 16Mb A19, 32Mb A20, 64Mb A21, 128Mb: A2 ...
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Address CS1# CS2 UB#, LB# WE# Data in Data out Figure 50. Write Cycle #2 (CS1# Controlled) Address CS1# CS2 UB#, LB# WE# Data in Data out Figure 51. Timing Waveform of Write Cycle(3) (CS2 Controlled) 130 ...
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Address CS1# CS2 UB#, LB# WE# Data in Data out Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled) Notes write occurs during the overlap (t with asserting UB# or ...
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Type 7 16Mb(1M word x 16-bit) 32Mb(2M word x 16-bit) 64Mb(4M word x 16-bit) CMOS 1M/2M/4M-Word x 16-bit pSRAM Features Asynchronous SRAM Interface Fast Access Time — max (16M — t ...
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Functional Description Mode CE2# Standby (Deselect) H Output Disable (Note 1) Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word Write Write (Upper Byte) Write (Lower Byte) Write ...
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Cycle # 3rd 4th 5th 6th The first cycle reads from the most significant address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the second or third cycle is written ...
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Absolute Maximum Ratings Item Voltage of V Supply Relative Voltage at Any Pin Relative to V Short Circuit Output Current Storage temperature WARNING: Semiconductor devices can be permanently damaged by ...
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DC Characteristics (Under Recommended Conditions Unless Otherwise Noted) Parameter Symbol Input Leakage Current Output Leakage OUT SS Current Output High Voltage ...
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Characteristics (Under Recommended Operating Conditions Unless Otherwise Noted) Read Operation Parameter Read Cycle Time CE1# Access Time OE# Access Time Address Access Time LB# / UB# Access Time Page Address Access Time ...
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AC Characteristics Write Operation Parameter Write Cycle Time Address Setup Time CE1# Write Pulse Width WE# Write Pulse Width LB#/UB# Write Pulse Width LB#/UB# Byte Mask Setup Time LB#/UB# Byte Mask Hold Time Write Recovery Time CE1# High Pulse Width ...
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Characteristics Power Down Parameters Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1# High Hold Time following CE2 High after Power Down Exit ...
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AC Characteristics AC Test Conditions Symbol Description V Input High Level IH V Input Low Level IL V Input Timing Measurement Level REF t Input Transition Time T AC Measurement Output Load Circuits V DD 0.1 μ ...
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Timing Diagrams Read Timings ADDRESS t ASC CE1# OE# LB#/ UB# DQ (Output) Note: This timing diagram assumes CE2=H and WE#=H. ADDRESS ADDRESS VALID CE1# Low t ASO OE# LB#/UB# DQ (Output) Note: ...
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Timing Diagrams t AX ADDRESS t AA CE1#, OE# Low t LB# UB# DQ1-8 (Output) DQ9-16 (Output) Note: This timing diagram assumes CE2=H and WE#=H. Figure 57. Read Timing #3 (LB#/UB# Byte Access) ADDRESS (A21-A3 ADDRESS ADDRESS VALID ...
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Timing Diagrams ADDRESS ADDRESS VALID (A21-A3 ADDRESS ADDRESS VALID (A2-A0 CE1# Low t t ASO OE OE LB#/UB# t OLZ t BLZ DQ (Output) Notes: 1. This ...
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Timing Diagrams ADDRESS t OHAH CE1# Low t AS WE# LB#, UB# t OES OE# t OHZ DQ (Input) Note:This timing diagram assumes CE2=H. Figure 61. Write Timing #2 (WE# Control) ADDRESS CE1# Low t AS WE# LB ...
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Timing Diagrams ADDRESS CE1# Low WE LB UB# DQ1-8 (Input) DQ9-16 (Input) Note: This timing diagram assumes CE2=H and OE#=H. Figure 63. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control) ...
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Read/Write Timings ADDRESS t t CHAH AS CE1 WE# UB#, LB# t OHCL OE# t CHZ READ DATA OUTPUT Notes: 1. This timing diagram assumes CE2=H. 2. Write address is valid from either CE1# or ...
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Read/Write Timings ADDRESS t OHAH CE1# Low t AS WE# t OES UB#, LB# OE# t OHZ READ DATA OUTPUT Notes: 1. This timing diagram assumes CE2=H. 2. CE1# can ...
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Read/Write Timings CE1# CE2 Notes: 1. The t specifies after V reaches specified minimum level. C2LH DD 2. For 32M only: The minimum and maximum V CE1# CE2 Notes: 1. The t specifies after ...
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Read/Write Timings CE1# OE# WE# Active (Read) Note: Both t and t define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes CHOX CHWX t (min) ...
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Revision Summary Revision A0 (June 9, 2004) Initial release. Revision A1 (July 19, 2004) Global Change Change all instances of FASL to Spansion Added Colophon text. Product Selector Guide Replaced “S71PL129JA0-9Z” with “S71PL129JA0-9P”. Ordering Information In Model Number section replaced ...
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Revision A8 (October 28, 2005) Product Selector Guide Updated to include two new part numbers Valid Combinations table Updated entire table Colophon The products described in this document are designed, developed and manufactured ...