PF38F1030W0ZBQ0S B93 Intel, PF38F1030W0ZBQ0S B93 Datasheet - Page 15

• Manufacturer Part Number: PF38F1030W0ZBQ0S B93
• Manufacturer: Intel

Specifications of PF38F1030W0ZBQ0S B93

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 1.
Datasheet
F[2:1]-VCC
F[2:1]-OE#
P-MODE
Symbol
F-VPEN
F-RST#
F-WE#
R-WE#
F-WP#
S-VCC
P-VCC
R-OE#
R-UB#
R-LB#
F-VPP
VCCQ
VSS
RFU
DU
Power
Power
Power
Power
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
Signal Descriptions (Sheet 2 of 2)
—
—
FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers. OE#-high disables
the flash output buffers, and places the flash outputs in High-Z.
F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and #3, and is
available only on SCSP combinations with two or three flash die and is RFU on SCSP combinations
with only one flash die.
RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the RAM output buffers. R-OE#-high
disables the RAM output buffers, and places the RAM outputs in High-Z.
R-OE# is only available on SCSP combinations with RAM die.
RAM UPPER/ LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM
high-order bytes on D[15:8], and R-LB#-low enables the RAM low-order bytes on D[7:0].
R-UB# and R-LB# are only available on SCSP combinations with either SRAM die or PSRAM die.
FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data
are latched on the rising edge of WE#.
RAM WRITE ENABLE: Low-true; R-WE# controls writes to the RAM die.
R-WE# is only available on SCSP combinations with RAM die.
FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of
the flash die. WP#-low enables the lock-down mechanism- locked down blocks cannot be unlocked
with software commands. WP#-high disables the lock-down mechanism, allowing locked down blocks
to be unlocked with software commands.
FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations.
RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array
mode.
FLASH PROGRAM/ ERASE POWER: A valid F-V
operations. Flash memory array contents cannot be altered when F-V
Erase/ program operations at invalid F-V
flash discrete product datasheet for additional details.
F-V
PSRAM MODE: Low-true; P-MODE is used to enter/exit low power mode.
Low power mode is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1,
38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0,
38F1030W0YTQE, 38F1030W0YBQE.
P-Mode is only available on SCSP combinations with PSRAM die.
FLASH LOGIC Power: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies
power to the core logic of flash die #2 and #3. Write operations are inhibited when F-V
Device operations at invalid F-V
F2-VCC is only available on SCSP combinations with two or three flash die, and is RFU on SCSP
combinations with only one flash die.
SRAM Power Supply: Supplies power to the SRAM die.
S-VCC is only available on SCSP combinations with SRAM die.
PSRAM Power Supply: Supplies power to the PSRAM die.
P-VCC is only available on SCSP combinations with PSRAM die.
FLASH OUTPUT-BUFFER Power: Supplies power for the I/O output buffers.
Ground: Connect to ground. Do not float any VSS connection.
Reserved for Future Use: Reserve for future device functionality/ enhancements.
Do Not Use: Do not connect to any other signal, or power supply; must be left floating.
PEN
Intel® Wireless Flash Memory (W18/W30 SCSP)
(Erase/Program/Block Lock Enables) is not available for W18/W30 products.
Order Number: 251407, Revision: 009
CC
voltages should not be attempted.
Intel® Wireless Flash Memory (W18/W30 SCSP)
Name and Function
PP
(V
PEN
) voltages should not be attempted. Refer to the
PP
voltage on this ball enables flash program/erase
PP
(V
PEN
) < V
PPLK
CC
(V
< V
June 2005
PENLK
LKO
).
.
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