AD9854ASQ Analog Devices Inc, AD9854ASQ Datasheet - Page 43

• Manufacturer Part Number: AD9854ASQ
• Manufacturer: Analog Devices Inc

Specifications of AD9854ASQ

• Lead Free Status / RoHS Status: Not Compliant

jumpers at W7 and W10 should be removed and 50 Ω test
signals applied at J4 and J5 inputs to the 50 Ω elliptic filters.
Users should refer to the schematic provided and to the following
sections to properly position the remaining shorting jumpers.
Observing the Unfiltered IOUT1 and the Unfiltered
IOUT2 DAC Signals
The unfiltered DAC outputs can be observed at J5 (the I, or
cosine, signal) and J4 (the Q, or control DAC, signal). The
procedure described simply routes the two 50 Ω terminated
analog DAC outputs to the SMB connectors and disconnects
any other circuitry. The raw DAC outputs may appear as a series of
quantized (stepped) output levels that may not resemble a sine
wave until they are filtered. The default 10 mA output current
develops a 0.5 V p-p signal across the on-board 50 Ω termination.
If the observation equipment offers 50 Ω inputs, the DAC
develops only 0.25 V p-p due to the double termination.
1.
2.
3.
4.
On the AD9852 evaluation board, IOUT2, the control DAC
output, is under user control through the serial or parallel ports.
The 12-bit, twos complement value(s) is/are written to the
control DAC register that sets the IOUT2 output to a static dc
level. Allowable hexadecimal values are 7FF (maximum) to 800
(minimum) with all 0s being midscale. Rapidly changing the
contents of the control DAC register (up to 100 MSPS) allows
IOUT2 to assume any waveform that can be programmed.
Observing the Filtered IOUT1 and the Filtered IOUT2
The filtered I and Q (or control) DAC outputs may be observed
at J6 (the I signal) and J7 (the Q, or control, signal). This places
the 50 Ω (input and output Z) low-pass filters in the I and Q
(or control) DAC pathways to remove images and aliased
harmonics and other spurious signals above approximately
120 MHz. These I and Q signals appear as nearly pure sine
waves and 90° out of phase with each other. These filters are
designed with the assumption that the system clock speed is at
or near maximum (300 MHz). If the system clock speed is
much less than 300 MHz, for example 200 MHz, it is possible
or inevitable that unwanted DAC products other than the
fundamental signal are passed by the low-pass filters.
1.
2.
3.
4.
5.
6.
Install shorting jumpers at W7 and W10.
Remove shorting jumper at W16.
Remove shorting jumper from the 3-pin W1 header.
Install shorting jumper on Pin 1 and Pin 2 (bottom two
pins) of the 3-pin W4 header.
If the AD9852 evaluation board is used, any reference to the
Q signal should be interpreted as meaning the control DAC.
Install shorting jumpers at W7 and W10.
Install shorting jumper at W16.
Install shorting jumper on Pin 1 and Pin 2 (bottom two
pins) of the 3-pin W1 header.
Install shorting jumper on Pin 1 and Pin 2 (bottom two
pins) of the 3-pin W4 header.
Install shorting jumper on Pin 2 and Pin 3 (bottom two
pins) of the 3-pin W2 and W8 headers.
Rev. D | Page 43 of 52
Observing the Filtered IOUT1 and the Filtered IOUT1
The filtered I DAC outputs may be observed at J6 (the true
signal) and J7 (the complementary signal). This places the
120 MHz low-pass filters in the true and complementary
output paths of the I DAC to remove images and aliased
harmonics and other spurious signals above approximately
120 MHz. These signals appear as nearly pure sine waves and
180° out of phase with each other. If the system clock speed is
much less than 300 MHz, for example 200 MHz, it is possible,
or inevitable, that unwanted DAC products other than the
fundamental signal are passed by the low-pass filters.
1.
2.
3.
4.
5.
To Connect the High Speed Comparator
To connect the high speed comparator to the DAC output
signals, either the quadrature-filtered output configuration
(AD9854 only) or the complementary-filtered output
configuration outlined in the previous section (for both the
AD9854 and the AD9852) can be chosen. Follow Steps 1
through 4 for either filtered configuration, as described
previously. Then install a shorting jumper on Pin 1 and Pin 2
(top two pins) of the 3-pin W2 and W8 headers. This reroutes
the filtered signals away from their output connectors (J6 and
J7) and to the 100 Ω configured comparator inputs. This sets up
the comparator for differential input without control of the
comparator output duty cycle. The comparator output duty
cycle should be close to 50% in this configuration.
The user can elect to change the R
to 1.95 kΩ to receive a more robust signal at the comparator
inputs. This decreases jitter and extends the operating range of
the comparator. This can be accomplished by installing a
shorting jumper at W6, which provides a second 3.9 kΩ chip
resistor (R20) in parallel with the provided R2. This boosts the
DAC output current from 10 mA to 20 mA and doubles the
peak-to-peak output voltage developed across the loads.
Single-Ended Configuration
To connect the high speed comparator in a single-ended
configuration that allows duty cycle or pulse width control
requires that a dc threshold voltage be present at one of the
comparator inputs. The user can supply this voltage using the
control DAC. A 12-bit, twos complement value is written to the
control DAC register that sets the IOUT2 output to a static dc
level. Allowable hexadecimal values are 7FF (maximum) to 800
(minimum) with all 0s being midscale. The IOUT1 channel
continues to output a filtered sine wave programmed by the
user. These two signals are routed to the comparator using W2
Install shorting jumpers at W7 and W10.
Install shorting jumper at W16.
Install shorting jumper on Pin 2 and Pin 3 (top two pins)
of the 3-pin W1 header.
Install shorting jumper on Pin 2 and Pin 3 (top two pins)
of the 3-pin W4 header.
Install shorting jumpers on Pin 2 and Pin 3 (bottom two
pins) of the 3-pin W2 and W8 headers.
SET
resistor, R2, from 3.9 kΩ
AD9854