AD9854ASQ Analog Devices Inc, AD9854ASQ Datasheet - Page 35

• Manufacturer Part Number: AD9854ASQ
• Manufacturer: Analog Devices Inc

Specifications of AD9854ASQ

• Lead Free Status / RoHS Status: Not Compliant

GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a serial communication cycle with the
AD9854. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9854, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9854 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is a read or write and the register
address to be acted upon.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9854. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9854
and the system controller. The number of data bytes transferred
in Phase 2 of the communication cycle is a function of the
register address. (Table 9 describes how many bytes must be
Table 9. Register Address vs. Data Bytes Transferred
Serial Register Address
0
1
2
3
4
5
6
7
8
9
A
B
SDIO
SDIO
SDO
CS
CS
Register Name
Phase Offset Tuning Word Register 1
Phase Offset Tuning Word Register 2
Frequency Tuning Word 1
Frequency Tuning Word 2
Delta frequency register
Update clock rate register
Ramp rate clock register
Control register
I path digital multiplier register
Q path digital multiplier register
Shaped on/off keying ramp rate register
Q DAC register
INSTRUCTION
INSTRUCTION
INSTRUCTION
INSTRUCTION
CYCLE
Figure 55. Using SDIO as an Input and SDO as an Output
CYCLE
BYTE
BYTE
Figure 54. Using SDIO as a Read/Write Transfer
DATA BYTE 1
DATA BYTE 1
Rev. D | Page 35 of 52
DATA TRANSFER
DATA TRANSFER
DATA TRANSFER
DATA BYTE 2
DATA BYTE 2
transferred.) The AD9854 internal serial I/O controller expects
every byte of the register being accessed to be transferred. Thus,
the user would want to write between I/O update clocks.
At the completion of any communication cycle, the AD9854
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. In
addition, an active high input on the IO RESET pin immediately
terminates the current communication cycle. After IO RESET
returns low, the AD9854 serial port controller requires the next
eight rising SCLK edges to be the instruction byte of the next
communication cycle.
All data input to the AD9854 is registered on the rising edge of
SCLK. All data is driven out of the AD9854 on the falling edge
of SCLK.
Figure 54 and Figure 55 show the general operation of the
AD9854 serial port.
DATA BYTE 3
DATA BYTE 3
Bytes Transferred
6
6
6
4
2
2
2
2
2
4
3
1
AD9854