AD9854ASQ Analog Devices Inc, AD9854ASQ Datasheet - Page 10

• Manufacturer Part Number: AD9854ASQ
• Manufacturer: Analog Devices Inc

Specifications of AD9854ASQ

• Lead Free Status / RoHS Status: Not Compliant

AD9854
Pin No.
20
21
22
29
30
31, 32, 37, 38, 44,
50, 54, 60, 65
33, 34, 39, 40, 41,
45, 46, 47, 53, 59,
62, 66, 67
36
42
43
48
49
51
52
55
56
61
64
68
69
70
71
Mnemonic
I/O UD CLK
WR/SCLK
RD/CS
FSK/BPSK/HOLD
OSK
AVDD
AGND
VOUT
VINP
VINN
IOUT1
IOUT1
IOUT2
IOUT2
DACBP
DAC R
PLL FILTER
DIFF CLK ENABLE
REFCLK
REFCLK
S/P SELECT
MASTER RESET
SET
Voltage Input Positive. The internal high speed comparator’s noninverting input.
Voltage Input Negative. The internal high speed comparator’s inverting input.
Selects serial programming mode (logic low) or parallel programming mode (logic high).
Description
Bidirectional I/O Update Clock. Direction is selected in control register. If selected as an input, a
rising edge transfers the contents of the I/O port buffers to the programming registers. If I/O UD CLK
is selected as an output (default), an output pulse (low to high) with a duration of eight system
clock cycles indicates that an internal frequency update has occurred.
Write Parallel Data to I/O Port Buffers. Shared function with SCLK. Serial clock signal associated
with the serial programming bus. Data is registered on the rising edge. This pin is shared with WR
when the parallel mode is selected. Mode is dependent on Pin 70 (S/P SELECT).
Read Parallel Data from Programming Registers. Shared function with CS. Chip-select signal
associated with the serial programming bus. Active low. This pin is shared with RD when parallel
mode is selected.
Multifunction pin according to the mode of operation selected in the programming control
register. In FSK mode, logic low selects F1 and logic high selects F2. In BPSK mode, logic low
selects Phase 1 and logic high selects Phase 2. In chirp mode, logic high engages the hold
function, causing the frequency accumulator to halt at its current location. To resume or
commence chirp mode, logic low is asserted.
Output Shaped Keying. Must first be selected in the programming control register to function. A
logic high causes the I and Q DAC outputs to ramp up from zero-scale to full-scale amplitude at a
preprogrammed rate. Logic low causes the full-scale output to ramp down to zero scale at the
preprogrammed rate.
Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND.
Connections for Analog Circuitry Ground Return. Same potential as DGND.
Internal High Speed Comparator’s Noninverted Output Pin. Designed to drive 10 dBm to 50 Ω
load as well as standard CMOS logic levels.
Unipolar Current Output of the I or Cosine DAC. (Refer to Figure 3.)
Complementary Unipolar Current Output of the I or Cosine DAC.
Complementary Unipolar Current Output of the Q or Sine DAC.
Unipolar Current Output of the Q or Sine DAC. This DAC can be programmed to accept external
12-bit data in lieu of internal sine data, allowing the AD9854 to emulate the AD9852 control DAC
function.
Common Bypass Capacitor Connection for Both I and Q DACs. A 0.01 μF chip capacitor from this
pin to AVDD improves harmonic distortion and SFDR slightly. No connect is permissible (slight
SFDR degradation).
Common Connection for Both I and Q DACs. Used to set the full-scale output current. R
Normal R
Provides the connection for the external zero compensation network of the REFCLK multiplier’s
PLL loop filter. The zero compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF
capacitor. The other side of the network should be connected to AVDD as close as possible to
Pin 60. For optimum phase noise performance, the REFCLK multiplier can be bypassed by setting
the bypass PLL bit in control register 1E.
Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK
and REFCLK (Pin 69 and Pin 68, respectively).
Complementary Differential Clock Signal (180° Out-of-Phase). User should tie this pin high or low
when single-ended clock mode is selected. Same signal levels as REFCLK.
Single-Ended Reference Clock Input (CMOS Logic Levels Required) or One of Two Differential
Clock Signals. In differential reference clock mode, both inputs can be CMOS logic levels or have
greater than 400 mV p-p square or sine waves centered about 1.6 V dc.
Initializes the serial/parallel programming bus to prepare for user programming; sets
programming registers to a do-nothing state defined by the default values listed in Table 7.
Active on logic high. Asserting MASTER RESET is essential for proper operation on power-up.
SET
range is from 8 kΩ (5 mA) to 2 kΩ (20 mA).
Rev. D | Page 10 of 52
SET
= 39.9/I
OUT
.