UCB1400BE128 NXP Semiconductors, UCB1400BE128 Datasheet - Page 48
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UCB1400BE128
Manufacturer Part Number
UCB1400BE128
Description
Manufacturer
NXP Semiconductors
Datasheet
1.UCB1400BE128.pdf
(64 pages)
Specifications of UCB1400BE128
Single Supply Voltage (typ)
3.3V
Single Supply Voltage (min)
3V
Single Supply Voltage (max)
3.6V
Package Type
LQFP
Lead Free Status / RoHS Status
Compliant
Philips Semiconductors
9397 750 09611
Product data
12.20 Feature Control/Status Register 2 (index 0x6C)
Table 50:
Register address: 0x6C; default: 0000
Table 51:
Bit
D15
D14 - D13
D12
D11 - D10
D5 - D4
D2 - D0
Bit
Symbol
Bit
Symbol
Feature Control/Status Register 2
Description of Feature Control/Status Register 2 bits
SMT
D15
D7
Symbol
SMT
SUEV1 -
SUEV0
AVE
AVEN1 -
AVEN0
SLP1 -
SLP0
EV2 - EV0
X
Rev. 02 — 21 June 2002
SUEV1
D14
D6
X
Type
RW
RW
RW
RW
RW
RW
SUEV0
SLP1
D13
D5
Description
Must be set to ‘0’ (other values reserved for testing
purposes only).
Must be set to ‘0’ (other values reserved for testing
purposes only).
If ‘1’, ADC Filter is enabled.
Must be set to ‘0’ (other values reserved for testing
purposes only).
Must be set to ‘0’ (other values reserved for testing
purposes only).
•
•
•
•
0: no Smart Low Power Mode.
On normal mode operation, all Codec input blocks
and PLL are ON.
1: Smart Low Power Mode on the Codec only.
On normal mode operation, only used input stage(s)
is/are ON. PLL remains ON all the time.
2: Smart Low Power Mode on the PLL only.
On normal mode operation, PLL is ON only when a
sample rate equal to 11.025, 22.05, or 44.1 kHz is
selected and the corresponding audio ADC or DAC
is not in power-down mode. Codec input blocks are
always ON.
3: Smart Low Power Mode on both Codec and PLL.
SLP0
Audio codec with touch screen controller
AVE
D12
D4
AVEN1
and power management monitor
D11
D3
X
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
AVEN0
D10
EV2
D2
UCB1400
EV1
D9
D1
X
47 of 63
EV0
D8
D0
X