STAC9752XXTAEB2X IDT, Integrated Device Technology Inc, STAC9752XXTAEB2X Datasheet
![](/photos/31/27/312712/48pin_tqfp_sml.jpg)
STAC9752XXTAEB2X
Specifications of STAC9752XXTAEB2X
Available stocks
Related parts for STAC9752XXTAEB2X
STAC9752XXTAEB2X Summary of contents
Page 1
... DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Description IDT's STAC9752/9753 are general purpose 20-bit, full duplex, audio CODECs conforming to the analog component specification of AC'97 (Audio CODEC 97 Component Specification Rev. 2.3). The STAC9752/9753 incorporate IDT's proprietary technology to achieve a DAC SNR in excess of 90dB. The DACs, ADCs and mixer ...
Page 2
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING TABLE OF CONTENTS 1. PRODUCT BRIEF ...................................................................................................................... 7 1.1. Description ........................................................................................................................................ 7 1.2. STAC9752/9753 Block Diagram ........................................................................................................ 8 1.3. Key Specifications ............................................................................................................................. 8 1.4. Related ...
Page 3
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 5.3.8. Slot 12: Audio GPIO Control Channel ............................................................................... 36 5.4. AC-Link Input Frame (SDATA_IN) ................................................................................................. 36 5.4.1. Slot 0: TAG ........................................................................................................................37 5.4.2. Slot 1: Status ...
Page 4
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.2.6. GPIO Pin Polarity/Type Register (4Eh) ............................................................................. 66 8.2.7. GPIO Pin Sticky Register (50h) ......................................................................................... 66 8.2.8. GPIO Pin Mask Register (52h) .......................................................................................... 67 8.2.9. ...
Page 5
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING LIST OF FIGURES Figure 1. Block Diagram ................................................................................................................................. 8 Figure 2. Cold Reset Timing ......................................................................................................................... 16 Figure 3. Warm Reset Timing ....................................................................................................................... 16 Figure 4. ...
Page 6
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING LIST OF TABLES Table 1. Clock Mode Configuration ............................................................................................................... 17 Table 2. Common Clocks and Sources ......................................................................................................... 18 Table 3. Recommended CODEC ID strapping ............................................................................................. ...
Page 7
... PRODUCT BRIEF 1.1. Description IDT's STAC9752/9753 are general purpose 20-bit, full duplex, audio CODECs conforming to the analog component specification of AC'97 (Audio CODEC 97 Component Specification Rev. 2.3). The STAC9752/9753 incorporate IDT's proprietary of 90dB. The DACs, ADCs and mixer are integrated with analog I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel ...
Page 8
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING ter volume slider to the proper physical output, and SoftEQ configurations. The fully parametric IDT SoftEQ can be initiated upon jack insertion and sensed impedance ...
Page 9
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 1.4. Related Materials • Product Brief • Reference Designs for MB, AMR, CNR, and ACR applications • Audio Precision Performance Plots 1.5. Additional Support Additional ...
Page 10
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 2. CHARACTERISTICS AND SPECIFICATIONS 2.1. Electrical Specifications 2.1.1. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the STAC9752/9753. These ...
Page 11
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 2.1.3. Power Consumption Digital Supply Current + 3.3V Digital Analog Supply Current (at Reset state Analog + 3.3V Analog Power Down Status (individually ...
Page 12
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 2.1.4. AC-Link Static Digital Specifications ( ºC, DVdd = 3.3V ± 5%, AVss=DVss=0V) ambient Parameter Input voltage range Low level input range High ...
Page 13
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Parameter HEADPHONE_OUT (32 HEADPHONE_OUT (10 K load) SNR (idle channel) (Note 5) DAC to LINE_OUT DAC in BYPASS Mode LINE / AUX / VIDEO to ...
Page 14
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 6. Peak-to-Peak Ripple over Passband meets ± 0.25dB limits, 48 KHz Sample Frequency. 7. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. ...
Page 15
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Parameter Power Supply Rejection Ratio (20 KHz) Any Analog Input to LINE_OUT Crosstalk (10 KHz Signal Frequency) Any Analog Input to LINE_OUT Crosstalk (1 KHz ...
Page 16
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 2.2. AC Timing Characteristics ( °C, AVdd = 3 ± 5%, DVdd = 3.3 V ± 5%, AVss=DVss=0 V; ...
Page 17
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 2.2.3. Clocks BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BLT_CLK high pulse width (Note ...
Page 18
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 2.2.5. Data Setup and Hold (50 pF external load) Setup to falling edge of BIT_CLK Hold from falling edge of BIT_CLK Output Valid Data from ...
Page 19
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 2.2.7. AC-Link Low Power Mode Timing End of Slot 2 to BIT_CLK, SDATA_IN low 2.2.8. ATE Test Mode Setup to trailing edge of RESET# (also ...
Page 20
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 3. TYPICAL CONNECTION DIAGRAM 0.1 µ ...
Page 21
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 3.1. Split Independent Power Supply Operation In PC applications, one power supply input to the STAC9752/9753 may be derived from a supply regulator and the ...
Page 22
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 3. ± 5% 0.1 µF 1 µF 25 AVdd1 12 PC_BEEP AUX_L 15 AUX_R 16 VIDEO_L ...
Page 23
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING CONTROLLER, CODEC AND AC-LINK 4. This section describes the physical and high-level functional aspects of the AC‘97 Controller to CODEC interface, referred to as AC-Link. ...
Page 24
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING AC'97 Clock Source RESET# Signal Asserted BIT_CLK Toggling? After RESET# Signal crystal present? oscillator present? oscillator presnent? Error condition - no clock source present The ...
Page 25
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING ates SYNC by dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This yields a 48 KHz SYNC signal whose period ...
Page 26
... CODEC ID Strapping Audio CODECs in the 48-pin package use pins 45 and 46 (defined as ID0# and ID1#) as strapping (i.e. configuration) pins to configure the CODEC ID. The ID0# and ID1# strapping bits adopt inverted polarity and default Primary (via a weak internal pullup) when left floating. This eliminates the need for external resistors for CODECs configured as Primary, and maintains backward compatibil- ity with existing layouts that treat pins 45 and 46 as “ ...
Page 27
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 4.6. AC-Link Power Management 4.6.1. Powering down the AC-Link The AC-Link signals can be placed in a low power mode. When the AC‘97’s Powerdown Register ...
Page 28
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 4.6.2.2. The STAC9752/9753 (running off Vaux) can trigger a wake event (PME#) by transitioning SDATA_IN from low to high and holding it high until either ...
Page 29
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 5. AC-LINK DIGITAL INTERFACE 5.1. Overview AC-Link is the 5 pin digital serial interface that links the AC‘97 CODEC to the Controller. The AC-Link protocol ...
Page 30
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Slot 0 SDATA_IN TAG 1 STATUS ADDR read port 2 STATUS DATA read port 3, 4 PCM L&R ADC record 5 Modem Line 1 ADC ...
Page 31
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING valid and non-valid slots? Each possible method brings with it different FIFO requirements. To achieve interoperability between AC‘97 Digital Controllers and CODECs designed by different ...
Page 32
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 1. Disable source of DAC samples in Controller 2. Set PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh When it wants to ...
Page 33
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING SYNC BIT_CLK SDATA_OUT End of previous audio frame A new AC-Link output frame begins with a low to high transition of SYNC. SYNC is synchronous ...
Page 34
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 5.3.1. Slot 0: TAG / CODEC ID Bit 1-0 Within slot ...
Page 35
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING AC-Link output frame slot 1 communicates control register address, and write/read command infor- mation to the STAC9752/9753. Bit 19 18:12 11:0 The first bit (MSB) ...
Page 36
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 5.3.8. Slot 12: Audio GPIO Control Channel AC-Link output frame slot 12 contains the audio GPIO control outputs. 5.4. AC-Link Input Frame (SDATA_IN) The AC-Link ...
Page 37
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 5.4.1. Slot 0: TAG Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the AC‘97 CODEC ...
Page 38
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING The AC-Link input frame Slot 1 tag bit is independent of the bit 11-2 slot request field, and ONLY indicates valid Status Address Port data ...
Page 39
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 5.4.8. Slots 7 & 8: Vendor Reserved The left and right ADC channels of the STAC9752/9753 may be assigned to slots 7&8 by Register 6Eh. ...
Page 40
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 5.5. AC-Link Interoperability Requirements and Recommendations 5.5.1. “Atomic slot” Treatment of Slot 1 Address and Slot 2 Data Command or Status Address and Data cannot ...
Page 41
... Vendor specific (enhanced input for docking, array mic, etc.) Vendor specific (enhanced input for docking, array mic, etc.) Vendor specific (enhanced input for docking, array mic, etc.) Provides optional interrupt capability for Audio CODEC (not usable when Audio Interrupt a modem is present) ...
Page 42
... STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit 19-1 Reserved (Audio CODEC will return zeros in bits 19-1) Optional: Assertion = 1 will cause interrupt to be propagated to Audio controller system interrupt. See 0 register 24h definition for enabling mechanism. ...
Page 43
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 6. STAC9752/9753 MIXER The STAC9752/9753 includes an analog mixer for maximum flexibility. The analog mixer is designed to the AC'97 specification to manage the playback ...
Page 44
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 7. MIXER FUNCTIONAL DIAGRAMS Figure 20. STAC9752 2-Channel Mixer Functional Diagram 2Ah:D5-D4 Slot Select 28h: D5-D4 Slot PCMOut Select PC_BEEP Phone 20h:D8 MIC1 MIC2 Analog ...
Page 45
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 7.1. Analog Mixer Input The mixer provides recording and playback of any audio sources or output mix of all sources. The STAC9752/9753 supports the following ...
Page 46
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 7.4. PC Beep Implementation The STAC9752/9753 offers 2 styles of PC BEEP, Analog and Digital. The digital PC Beep is a new feature added to ...
Page 47
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8. PROGRAMMING REGISTERS Address 00h Reset 02h Master Volume 04h HP_OUT Mixer Volume 06h Master Volume MONO 0Ah PC Beep Mixer Volume 0Ch Phone Mixer ...
Page 48
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Address 72h Analog Current Adjust 74h EAPD Access 78h High Pass Filter Bypass 7Ah Reserved 7Ch Vendor ID1 7Eh Vendor ID2 Note: * depends upon ...
Page 49
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value 12 4:0 0 8.1.3. Headphone Volume Registers (04h) Default: 8000h D15 ...
Page 50
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.1.4. Master Volume MONO (06h) Default: 8000h D15 D14 Mute D7 RESERVED Bit(s) Reset Value 4:0 0 IDT™ TWO-CHANNEL, ...
Page 51
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.1.5. PC BEEP Volume (0Ah) Default: 0000h Additional information on the PC Beep can be found in Section 7.4: page46. D15 D14 Mute D7 F2 ...
Page 52
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.1.7. Mic Volume (Index 0Eh) Default: 8008h. D15 D14 Mute D7 RESERVED BOOSTEN Bit(s) Reset Value 4:0 ...
Page 53
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.1.9. CD Volume (Index 12h) Default: 8808h. D15 D14 Mute D7 RESERVED Bit(s) Reset Value 15 1 14:13 0 12:8 0 7:5 0 4:0 0 ...
Page 54
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.1.11. Aux Volume (Index 16h) Default: 8808h. D15 D14 Mute D7 RESERVED Bit(s) Reset Value 15 1 14:13 0 12:8 0 7:5 0 4:0 0 ...
Page 55
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value 7:5 0 4:0 0 8.1.13. Record Select (1Ah) Default: 0000h (corresponding to Microphone in) Used to select the record source independently for ...
Page 56
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value 11:8 0 7:4 0 3:0 0 8.1.15. General Purpose (20h) Default: 0000h D15 D14 POP BYP RESERVED D7 LOOPBACK Reset Bit(s) Value ...
Page 57
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value 15:4 0 3:2 0 1:0 0 This register is used to control the 3D stereo enhancement function, IDT Surround 3D (SS3D), built ...
Page 58
... Read / Write I0 GPI functionality. Some AC’97 2.2 compliant controllers will not likely support audio CODEC interrupt infrastructure. In either case, S/W should poll the interrupt status after initiating a sense cycle and wait for Sense Cycle Max Delay to determine if an interrupting event has occurred. ...
Page 59
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value 8.1.18.1. The lower half of this register is read only ...
Page 60
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING The Extended Audio ID register is a read only register except for bits D4 and D5. ID1 and ID0 echo the configuration of the CODEC ...
Page 61
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.1.20. Extended Audio Control/Status (2Ah) Default: 0400h* (*default depends on CODEC ID) D15 D14 VCFG D7 RESERVED Note: If pin 48 is held high at ...
Page 62
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value 8.1.20.1. The Extended Audio Status Control register also contains one active bit to enable or disable the Variable ...
Page 63
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING CODEC ID 00 2-ch Primary w/SPDIF 01 2-ch Dock CODEC w/SPDIF 10 +2-ch Surr w/ SPDIF 11 +2-ch Cntr/LFE w/ SPDIF 8.1.21. PCM DAC Rate ...
Page 64
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.1.24. SPDIF Control (3Ah) Default: 2000h D15 D14 V DRS D7 CC3 CC2 Bit(s) Reset Value 13: ...
Page 65
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.2.2. GPIO Pin Definitions GPIO pins are programmable to have input/output functionality. The data values (status) for these pins are all in one register with ...
Page 66
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.2.5. GPIO Pin Configuration Register (4Ch) Default: 0003h D15 D14 D7 Bit(s) Access 15:2 Read Only 1 Read / Write 0 Read / Write 8.2.6. ...
Page 67
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.2.8. GPIO Pin Mask Register (52h) Default: 0000h D15 D14 D7 Bit(s) Access 15:2 Read Only 1 Read / Write 0 Read / Write 8.2.9. ...
Page 68
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.3. Extended CODEC Registers Page Structure Definition Registers 60h-68h are the Extended CODEC Registers: These registers allow for the defi- nition of further capabilities. These ...
Page 69
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.4. STAC9752/9753 Paging Registers The AC’97 Specification Rev 2.3 uses a paging mechanism in order to increase the number of regis- ters. The registers currently ...
Page 70
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value 12-8 7-0 8.4.2. PCI SVID (62h Register 24h must be set to Page 01h to access this register. Default: FFFFh D15 D14 ...
Page 71
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.4.4. Function Select (66h Register 24h must be set to Page 01h to access this register. Default: 0000h D15 D14 D7 RESERVED Bit(s) Reset Value ...
Page 72
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.4.5. Function Information (68h Register 24h must be set to Page 01h to access this register. Default: 00xxh, see table 22: page73. D15 D14 G4 ...
Page 73
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value Reg 66h Function Code 00h Line Out 01h Headphone Out All other Function Codes G[4:0] 00000 ...
Page 74
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Default: 0000h D15 D14 D7 Bit(s) Reset Value 15 8.4.7. Sense Details (6Ah Register 24h must be set ...
Page 75
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value 7-6 5-0 Reported Value Bh-Eh Fh Reported Value ...
Page 76
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.4.8. Revision Code (6Ch) To access Register 6Ch, Page 00h must be selected in Register 24h. Default: 00xxh D15 D14 D7 Bit(s) Reset Value 15:8 ...
Page 77
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value 8.4.10. Analog Current Adjust (72h) To unlock Register 72h, write 0xABBA to Register 70h. ...
Page 78
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Bit(s) Reset Value 15 0 14: 10 8.4.12. High Pass Filter Bypass (78h) To unlock ...
Page 79
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 8.5. Vendor ID1 and ID2 (Index 7Ch and 7Eh) These two registers contain four 8-bit ID codes. The first three codes have been assigned by ...
Page 80
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 9. LOW POWER MODES The STAC9752/9753 is capable of operating at reduced power when no activity is required. The state of power down is controlled ...
Page 81
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Figure 23. Powerdown/Powerup flow with analog still alive Normal PR0=0 & ADC=1 Figure 23 illustrates a state when all the mixers should work with the ...
Page 82
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 10. MULTIPLE CODEC SUPPORT The STAC9752/9753 provides support for the multi-CODEC option according to the Intel AC'97, rev 2.3 specification. By definition, there can be ...
Page 83
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 10.2. Secondary CODEC Register Access Definitions The AC'97 Digital Controller can independently access Primary and Secondary CODEC registers by using a 2-bit CODEC ID field ...
Page 84
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 11. TESTABILITY The STAC9752/9753 has two test modes. One is for ATE in-circuit test and the other is restricted for manufacturer’s internal use. The STAC9752/9753 ...
Page 85
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 12. PIN DESCRIPTION MONO_OUT 37 HP_OUT_L 39 HP_COMM 40 HP_OUT_R 41 Pin 48: To Enable SPDIF, use -10 K external pulldown. To ...
Page 86
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 12.1. Digital I/O These signals connect the STAC9752/9753 to its AC'97 controller counterpart, an external crystal, multi-CODEC selection and external audio amplifier. Pin Name XTL_IN ...
Page 87
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 12.2. Analog I/O These signals connect the STAC9752/9753 to analog sources and sinks, including microphones and speakers. Pin Name PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R ...
Page 88
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 12.3. Filter/References These signals are connected to resistors, capacitors, or specific voltages. Signal Name VREF VREFOUT AFILT1 AFILT2 CAP2 12.4. Power and Ground Signals Pin ...
Page 89
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 13. ORDERING INFORMATION Part Number STAC9752XXTAEyyX 48-pin RoHS QFP 7mm x 7mm x 1.4mm STAC9753XXTAEyyX 48-pin RoHS QFP 7mm x 7mm x 1.4mm yy = ...
Page 90
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 15. SOLDER REFLOW PROFILE 15.1. Standard Reflow Profile Data Note: These devices can be hand soldered at 360 FROM: IPC / JEDEC J-STD-020C “Moisture/Reflow Sensitivity ...
Page 91
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 15.2. Pb Free Process - Package Classification Reflow Temperatures Package Type IDT™ TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK ...
Page 92
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 16. APPENDIX A: PROGRAMMING REGISTERS Reg # Name D15 D14 00h Reset RSRVD SE4 02h Master Volume Mute RSRVD HP_OUT 04h Mute RSRVD HPL5 Mixer ...
Page 93
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Reg # Name D15 D14 6Ch Page 01h 6Eh Analog Special RESERVED 6Eh Page 01h 70h 72h Analog Current Adjust 74h EAPD Access EAPD RESERVED ...
Page 94
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING 17. REVISION HISTORY Revision Date -Removed “Preliminary” tag on front page. -Removed BIT_CLK as an input option from clocking table, it was incorrectly included in ...
Page 95
STAC9752/9753 TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Innovate with IDT audio for high fidelity. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley ...