ADAV803AST Analog Devices Inc, ADAV803AST Datasheet - Page 36

no-image

ADAV803AST

Manufacturer Part Number
ADAV803AST
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADAV803AST

Single Supply Voltage (typ)
3.3V
Single Supply Voltage (min)
3V
Single Supply Voltage (max)
3.6V
Package Type
LQFP
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADAV803ASTZ
Manufacturer:
ADI
Quantity:
163
Part Number:
ADAV803ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADAV803ASTZ-REEL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADAV803
Receiver Configuration 2—Address 0001010 (0x0A)
Table 33. Receiver Configuration 2 Register Bit Map
7
RxMUTE
Table 34. Receiver Configuration 2 Register Bit Descriptions
Bit Name
RxMUTE
SP_PLL
SP_PLL_SEL[1:0]
NO NONAUDIO
NO_VALIDITY
6
SP_PLL
Description
Hard-mutes the audio output for the AES3/S/PDIF receiver.
AES3/S/PDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock.
Selects one of the four serial ports as the reference clock to the PLL when SP_PLL is set.
When the NO NONAUDIO bit is set, data from the AES3/S/PDIF receiver is not allowed into the sample rate converter
(SRC). If the NO NONAUDIO data is due to DTS, AAC, and so on, as defined by the IEC61937 standard, then the data
from the AES3/S/PDIF receiver is not allowed into the SRC regardless of the state of this bit.
When the NO_VALIDITY bit is set, data from the AES3/S/PDIF receiver is not allowed into the SRC.
0 = AES3/S/PDIF receiver is not muted.
1 = AES3/S/PDIF receiver is muted.
0 = Left/right clock generated from the AES3/S/PDIF preambles is the reference clock to the PLL.
1 = Left/right clock from one of the serial ports is the reference clock to the PLL.
00 = Playback port is selected.
01 = Auxiliary input port is selected.
10 = Record port is selected.
11 = Auxiliary output port is selected.
0 = AES3/S/PDIF receiver data is sent to the SRC.
1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO NONAUDIO bit is set.
0 = AES3/S/PDIF receiver data is sent to the SRC.
1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO_VALIDITY bit is set.
5
SP_PLL_ SEL1
4
SP_PLL_ SEL0
Rev. A | Page 36 of 60
Reserved
3
2
Reserved
1
NO NONAUDIO
0
NO_VALIDITY

Related parts for ADAV803AST