ADAV803AST Analog Devices Inc, ADAV803AST Datasheet - Page 30

• Manufacturer Part Number: ADAV803AST
• Manufacturer: Analog Devices Inc

Specifications of ADAV803AST

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

ADAV803
INTERFACE CONTROL
The ADAV803 has a dedicated control port to allow the internal
registers of the ADAV803 to be accessed. Each of the internal
registers is eight bits wide. Where bits are described as reserved
(RES), these bits should be programmed as zero.
I
The I
consisting of a clock line, SCL, and a data line, SDA. SDA is
bidirectional; the ADAV803 drives SDA to either acknowledge
the master, ACK, or send data during a read operation. The
SDA pin for the I
a 1 kΩ pull-up resistor. A write or read access occurs when the
SDA line is pulled low while the SCL line is high, indicated by
START in the timing diagrams. SDA is allowed to change only
when SCL is low, except when a start or stop condition occurs,
as shown in Figure 53 and Figure 54. The I
both standard (100 kbps) and fast (400 kbps) modes as defined
by the I
The first eight bits of the access consist of the device address
and the R/W bit. The device address consists of an internal
built-in address (0b00100) and two address pins, AD1 and
AD0. The two address pins allow up to four ADAV803s to be
used in a system.
2
C INTERFACE
2
C interface of the ADAV803 is a 2-wire interface
2
C standards.
SCK
SDA
START BY
MASTER
2
C port is an open-drain collector that requires
0
0
1
CHIP ADDRESS BYTE
0
FRAME 1
2
C interface supports
0
Figure 53. Writing to the DAC Left Volume Register in I
(CONTINUED)
(CONTINUED)
AD1
SCK
SDA
AD0
Rev. A | Page 30 of 60
R/W
D7
ADAV803
ACK. BY
D6
1
Initiating a write operation to the ADAV803 involves sending a
start condition and then sending the device address with the
R/W set low. The ADAV803 responds by issuing an ACK to
indicate that it has been addressed. The user then sends a
second frame telling the ADAV803 which register is required to
be written to. The 7-bit register address is left-shifted to make
the eight bits that the frame requires. Another ACK is issued by
the ADAV803. Finally, the user can send another frame with the
eight data bits required to be written to the register. A third
ACK is issued by the ADAV803, after which the user can send a
stop condition to complete the data transfer.
A read operation requires that the user first write to the
ADAV803 to point to the correct register and then read the
data. This is achieved by sending a start condition followed by
the device address frame, with R/W low, and then the register
address frame. Following the ACK from the ADAV803, the user
must issue a repeated start condition. This is identical to a start
condition. The next frame is the device address with R/W set
high. On the next frame, the ADAV803 outputs the register data
on the SDA line. A stop condition completes the read operation.
Figure 53 and Figure 54 show examples of writing to and read-
ing from the DAC left volume register (Address 0b1101000).
D5
1
D4
0
REGISTER ADDRESS BYTE
DATA BYTE TO
FRAME 3
ADAV803
D3
1
2
C
FRAME 2
D2
0
D1
0
D0
0
ADAV803
ACK. BY
X
STOP BY
MASTER
ADAV803
ACK. BY