ADAV803AST Analog Devices Inc, ADAV803AST Datasheet - Page 23

• Manufacturer Part Number: ADAV803AST
• Manufacturer: Analog Devices Inc

Specifications of ADAV803AST

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

S/PDIF TRANSMITTER AND RECEIVER
The ADAV803 contains an integrated S/PDIF transmitter and
receiver. The transmitter consists of a single output pin,
DITOUT, on which the biphase encoded data appears. The
S/PDIF transmitter source can be selected from the different
blocks making up the ADAV803. Additionally, the clock source
for the S/PDIF transmitter can be selected from the various
clock sources available in the ADAV803.
The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts
the S/PDIF input data stream. The DIRIN pin can be configured
to accept a digital input level, as defined in the Specifications
section, or an input signal with a peak-to-peak level of 200 mV
minimum, as defined by the IEC 60958-3 specification. DIR_LF
is a loop filter pin, required by the internal PLL, which is used
to recover the clock from the S/PDIF data stream.
The components shown in Figure 42 form a loop filter, which
integrates the current pulses from a charge pump and produces
a voltage that is used to tune the VCO of the clock recovery
PLL. The recovered audio data and audio clock can be routed to
the different blocks of the ADAV803, as required. Figure 39
shows a conceptual diagram of the DIRIN block.
SPDIF
C*
*EXTERNAL CAPACITOR IS ONLY REQUIRED
DIRIN
FOR VARIABLE LEVEL SPDIF INPUTS.
LEVEL
DC
Figure 39. DIRIN Block
REG 0x7A
BIT 4
COMPARATOR
44.1kHz
44.1kHz
48kHz
32kHz
48kHz
32kHz
256
384
256
384
256
512
RECEIVER
SPDIF
PLL1 MCLK
PLL2 MCLK
REG 0x75
BITS[3:2]
REG 0x75
BIT 1
REG 0x75
BIT 5
REG 0x75
BITS[7:6]
REG 0x74
BIT 0
Figure 38. PLL Clocking Scheme
REG 0x75
REG 0x75
Rev. A | Page 23 of 60
BIT 0
BIT 4
×2
×2
FS3
FS1
FS2
REG 0x77
REG 0x77
BITS[2:1]
BIT 0
÷2
÷2
÷2
CHANNEL STATUS
AND USER BITS
AUXILIARY IN
Figure 40. Digital Output Transmitter Block Diagram
PLAYBACK
Figure 41. Digital Input Receiver Block Diagram
6.8nF
PLLINT1
PLLINT2
ADC
SRC
Figure 42. DIR Loop Filter Components
DIR
PLL1
PLL2
AVDD
DIRIN
REG 0x63
BITS[2:0]
DIR
SYSCLK1
SYSCLK2
SYSCLK3
3.3kΩ
100nF
DIT
INPUT
DIR_LF
DIR BLOCK
AUDIO
DATA
RECOVERED
CLOCK
CHANNEL STATUS/
USER BITS
DIT
ADAV803
DITOUT