IDT92HD71B8X3NLGXB3X IDT, Integrated Device Technology Inc, IDT92HD71B8X3NLGXB3X Datasheet - Page 19

• Manufacturer Part Number: IDT92HD71B8X3NLGXB3X
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT92HD71B8X3NLGXB3X

• Lead Free Status / RoHS Status: Compliant

4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
1
2
3
4
Power State
D0
D1
D2
D3
D0-D3
92HD71B8
4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
Digital Mics
Yes
Yes
Yes
Yes
No
DMIC Widget
Single Edge
Double Edge on
either DMIC_0 or 1
OR
Single Edge on
DMIC_0 and 1
Double Edge on
one DMIC pin and
Single Edge on the
second DMIC pin.
Double Edge
Enabled?
Data Sample
Clock Capable
Clock Disabled
Clock Disabled
Clock Disabled
Clock Disabled
Table 9. DMIC_CLK and DMIC_0,1 Operation During Power States
DMIC_CLK
Output
0, or 1
0, or 1
0, or 1
0, or 1
ADC Conn.
Table 8. Valid Digital Mic Configurations
Input Capable
Input Disabled
Input Disabled
Input Disabled
Input Disabled
DMIC_0,1
Available on either DMIC_0 or DMIC_1
Both ADC Channels produce data, may be in phase or out by 1/2 DMIC_CLK
period depending upon external configuration and timing
Available on either DMIC_0 or DMIC_1, External logic required to support
sampling on a single Digital Mic pin channel on rising edge and second Digital Mic
right channel on falling edge of DMIC_CLK for those digital microphones that don’t
support alternative clock edge capability. If both DMIC_0 and DMIC_1 are used to
support 2 digital microphones, 2 separate ADC units will be used, however, this
configuration is not recommended since it consumes two stereo ADC resources.
Requires both DMIC_0 AND DMIC_1, External logic required to support sampling
on a single Digital Mic pin channel on rising edge and second Digital Mic right
channel on falling edge of DMIC_CLK for those digital microphones that don’t
support alternative clock edge capability. Two ADC units are required to support
this configuration
Connected to DMIC_0 and DMIC_1, External logic required to support sampling
on a single Digital Mic pin channel on rising edge and second Digital Mic right
channel on falling edge of DMIC_CLK for those digital microphones that don’t
support alternative clock edge capability. Two ADC units are required to support
this configuration
19
DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1
Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low
DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1
Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low
DMIC_CLK Remains Low
DMIC_CLK Remains Low
DMIC_CLK is HIGH-Z with Weak Pull-down
Notes
92HD71B8
Notes
PC AUDIO
V 1.0, 01/08