SAA7105E/V1/G-T NXP Semiconductors, SAA7105E/V1/G-T Datasheet - Page 7

• Manufacturer Part Number: SAA7105E/V1/G-T
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G-T

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,518

Philips Semiconductors
Notes
1. Pin type: I = input, O = output, S = supply, pu = pull-up.
2. In accordance with the “IEEE1149.1” standard the pins TDI, TMS, TCK and TRST are input pins with an internal
3. For board design without boundary scan implementation connect TRST to ground.
4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test
5. The pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1.
2004 Mar 04
VSM
HSM_CSYNC
TCK
SCL
HSVGC
reserved
VSVGC
PIXCLKI
PD3
V
TVD
FSVGC
SDA
CBO
PIXCLKO
PD2
PD1
PD0
DDD1
Digital video encoder
pull-up resistor and TDO is a 3-state output pin.
Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
SYMBOL
E12
PIN
F12
G1
G2
G3
G4
D7
D8
E1
E2
E3
H1
H2
H3
F1
F2
F3
F4
TYPE
I/pu
I/O
I/O
I/O
I/O
I/O
O
O
O
O
S
I
I
I
I
I
I
(1)
vertical synchronization output to monitor (non-interlaced auxiliary
RGB)
horizontal synchronization output to monitor (non-interlaced
auxiliary RGB) or composite sync for RGB-SCART
test clock input for BST; note 2
I
horizontal synchronization output to VGC (optional input); note 5
to be reserved for future applications
vertical synchronization output to VGC (optional input); note 5
pixel clock input (looped through)
MSB
pin assignment
digital supply voltage 1 for pins PD11 to PD0, PIXCLKI, PIXCLKO,
FSVGC, VSVGC, HSVGC, CBO and TVD
interrupt if TV is detected at DAC output
frame synchronization output to Video Graphics Controller (VGC)
(optional input); note 5
I
composite blanking output to VGC; active LOW; note 5
pixel clock output to VGC
MSB
pin assignment
MSB
pin assignment
MSB
pin assignment
2
2
C-bus serial clock input
C-bus serial data input/output
7
4 with C
5 with C
6 with C
7 with C
B
B
B
B
-Y-C
-Y-C
-Y-C
-Y-C
R
R
R
R
4 : 2 : 2; see Tables 9 to 14 for
4 : 2 : 2; see Tables 9 to 14 for
4 : 2 : 2; see Tables 9 to 14 for
4 : 2 : 2; see Tables 9 to 14 for
DESCRIPTION
SAA7104E; SAA7105E
Product specification