SAA7120H/V2,557 NXP Semiconductors, SAA7120H/V2,557 Datasheet - Page 27

• Manufacturer Part Number: SAA7120H/V2,557
• Manufacturer: NXP Semiconductors

Specifications of SAA7120H/V2,557

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
8.1
1. The HPLL increment is not evaluated by the
2. The SAA7120H; SAA7121H generates the subcarrier
3. The PAL bit indicates the line with inverted (R
4. If the reset bit is enabled (RTCE = 1; DECPH = 1;
5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the
2002 Oct 11
handbook, full pagewidth
Digital video encoder
RTCI
(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment.
(2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit.
(3) Sequence bit: PAL: 0 = (R
(4) Reset bit: only from SAA7111 and SAA7112 decoder.
(5) FISE bit: 0 = 50 Hz, 1 = 60 Hz.
(6) Odd/even bit: odd_even from external.
(7) Colour detection: 0 = no colour detected, 1 = colour detected.
(8) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.
SAA7120H; SAA7121H.
frequency from the FSCPLL increment if enabled
(see item 7.).
component of colour difference signal.
PHRES = 00), the phase of the subcarrier is reset in
each line whenever the reset bit of RTCI input is set to
logic 1.
SAA7120H; SAA7121H takes this bit instead of the
FISE bit in subaddress 61H.
Explanation of RTCI data bits
HIGH-to-LOW transition
count start
128
time slot:
not used in SAA7120H/21H
LOW
Y) line normal, 1 = (R
0 1
13
increment
HPLL
(1)
14
0
reserved
Y) line inverted; NTSC: 0 = no change.
4 bits
19
Fig.9 RTCI timing.
22
Y)
27
6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1),
7. If the colour detection bit is enabled (RTCE = 1;
the SAA7120H; SAA7121H ignores its internally
generated odd/even flag and takes the odd/even bit
from RTCI input.
DECCOL = 1) and no colour was detected (colour
detection bit = 0), the subcarrier frequency is
generated by the SAA7120H; SAA7121H. In the other
case (colour detection bit = 1) the subcarrier
frequency is evaluated out of FSCPLL increment.
If the colour detection bit is disabled (RTCE = 1;
DECCOL = 0), the subcarrier frequency is evaluated
out of FSCPLL increment, independent of the colour
detection bit of RTCI input.
FSCPLL increment
sample
valid
sample
invalid
(2)
SAA7120H; SAA7121H
8/LLC
reserved
3 bits
Product specification
64
0
67
68
MBH789
(3)
69
(4)
(5)
72 74
(6)
(8)
(7)