SAA7120H/V2,557 NXP Semiconductors, SAA7120H/V2,557 Datasheet - Page 18

• Manufacturer Part Number: SAA7120H/V2,557
• Manufacturer: NXP Semiconductors

Specifications of SAA7120H/V2,557

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
Table 24 Logic levels and function of SRCV1
Table 25 Subaddresses 6CH and 6DH
Table 26 Subaddress 6DH
Table 27 Subaddress 6EH
Table 28 Logic levels and function of PHRES
2002 Oct 11
HTRIG
VTRIG
SBLBN
PHRES
FLC
DATA BYTE
DATA BYTE
DATA BYTE
Digital video encoder
PHRES1
SRCV11
0
0
1
1
0
0
1
1
DATA BYTE
DATA BYTE
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
sets the vertical trigger phase related to signal on RCV1 input
PHRES0
SRCV10
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases
delays of all internally generated timing signals; reference mark: analog output horizontal sync
(leading slope) coincides with active edge of RCV used for triggering at HTRIG = 398H (398H)
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH)
LOGIC
LEVEL
0
1
0
1
0
1
0
1
0
1
vertical blanking is defined by programming of FAL and LAL; default after reset
vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz)
selects the phase reset mode of the colour subcarrier generator; see Table 28
field length control; see Table 29
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
reset every two lines
reset every eight fields
reset every four fields
AS OUTPUT
FSEQ
VS
FS
AS INPUT
FSEQ
VS
FS
18
DESCRIPTION
DESCRIPTION
vertical sync each field; default after reset
frame sync (odd/even)
field sequence, vertical sync every fourth field (PAL = 0)
or eighth field (PAL = 1)
not applicable
DESCRIPTION
DESCRIPTION
SAA7120H; SAA7121H
FUNCTION
Product specification