ADV7340BSTZ Analog Devices Inc, ADV7340BSTZ Datasheet - Page 30

• Manufacturer Part Number: ADV7340BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7340BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7340/ADV7341
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV7340/ADV7341 via the MPU port, except for registers that
are specified as read-only or write-only registers.
The subaddress register determines which register the next
read or write operation accesses. All communication through
the MPU port starts with an access to the subaddress register.
A read/write operation is then performed from/to the target
address, which increments to the next address until the
transaction is complete.
Table 17. Register 0x00
SR7 to
SR0
0x00
Table 18. Register 0x01 to Register 0x09
SR7 to
SR0
0x01
Register
Mode select
Register
Power
mode
Bit Description
Sleep mode. With this control enabled, the current
consumption is reduced to μA level. All DACs and the internal
PLL circuits are disabled. Registers can be read from and
written to in sleep mode.
PLL and oversampling control. This control allows the internal
PLL 1 circuit to be powered down and the oversampling to be
switched off.
DAC 3: power on/off.
DAC 2: power on/off.
DAC 1: power on/off.
DAC 6: power on/off.
DAC 5: power on/off.
DAC 4: power on/off.
DDR clock edge alignment
(only used for ED
DDR modes)
Reserved.
Input mode (see Subaddress
0x30, Bits[7:3] for ED/HD
standard selection)
Y/C/S bus swap
Bit Description
Reserved.
2
and HD
7
0
1
Rev. A | Page 30 of 108
6
0
0
0
0
1
1
1
1
5
0
0
1
1
0
0
1
1
Bit Number
4
0
1
0
1
0
1
0
1
3
0
REGISTER PROGRAMMING
Table 17 to Table 35 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines to or
from which register the operation takes place.
1
2
0
0
1
1
1
0
1
0
1
0
0
7
0
1
Register Setting
Chroma clocked in on rising clock edge;
luma clocked in on falling clock edge
Reserved
Reserved
Luma clocked in on rising clock edge;
chroma clocked in on falling clock edge
SD input only
ED/HD-SDR input only
ED/HD-DDR input only
SD and ED/HD-SDR
SD and ED/HD-DDR
Reserved
Reserved
ED only (at 54 MHz)
Allows data to be applied to data ports in
various configurations (SD feature only)
6
0
1
5
0
1
Bit Number
4
0
1
3
0
1
2
0
1
1
0
1
0
0
1
Register
Setting
Sleep
mode off
Sleep
mode on
PLL 1 on
PLL 1 off
DAC 3 off
DAC 3 on
DAC 2 off
DAC 2 on
DAC 1 off
DAC 1 on
DAC 6 off
DAC 6 on
DAC 5 off
DAC 5 on
DAC 4 off
DAC 4 on
Reset
Value
0x12
Reset
Value
0x00