ADV7340BSTZ Analog Devices Inc, ADV7340BSTZ Datasheet - Page 102

• Manufacturer Part Number: ADV7340BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7340BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7340/ADV7341
Table 97. 30-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 98. 30-Bit 525p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 99. 30-Bit 525p RGB In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
0x35
Table 100. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Setting
0x02
0x1C
0x10
0x10
0x04
0x01
0x2C
Setting
0x02
0x1C
0x10
0x10
0x00
0x01
0x2C
Setting
0x02
0x1C
0x10
0x10
0x00
0x01
0x2C
0x02
Setting
0x02
0x1C
0x20
0x1C
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
RGB input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
Rev. A | Page 102 of 108
Table 101. 10-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Table 102. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 103. 10-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 104. 20-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
0x02
0x1C
0x20
0x18
0x01
0x6C
0x02
0x1C
0x20
0x10
0x1C
0x01
0x6C
0x02
0x1C
0x20
0x10
0x18
0x01
0x6C
0x02
0x1C
0x10
0x1C
0x01
0x6C
Setting
Setting
Setting
Setting
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p at 50 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
Pixel data valid.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
Pixel data valid.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled (10 × 2 = 20-bit).