ADV7340BSTZ Analog Devices Inc, ADV7340BSTZ Datasheet - Page 106

• Manufacturer Part Number: ADV7340BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7340BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7340/ADV7341
Table 124. 30-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 125. 30-Bit 720p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 126. 30-Bit 720p RGB In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
0x35
Table 127. 10-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Setting
0x02
0x1C
0x10
0x10
0x2C
0x01
0x2C
Setting
0x02
0x1C
0x10
0x10
0x28
0x01
0x2C
Setting
0x02
0x1C
0x10
0x10
0x28
0x01
0x2C
0x02
Setting
0x02
0x1C
0x20
0x6C
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
RGB input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.
Rev. A | Page 106 of 108
Table 128. 10-Bit 1080i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Table 129. 10-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 130. 10-Bit 1080i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 131. 20-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
0x02
0x1C
0x20
0x68
0x01
0x6C
0x02
0x1C
0x20
0x10
0x6C
0x01
0x6C
0x02
0x1C
0x20
0x10
0x68
0x01
0x6C
0x02
0x1C
0x10
0x6C
0x01
0x6C
Setting
Setting
Setting
Setting
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
1080i at 30 Hz/29.97 Hz. HSYNC/
VSYNC synchronization. EIA-770.3
output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. HSYNC/
VSYNC synchronization. EIA-770.3
output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled (10 × 2 = 20-bit).