SAA7129HV1 NXP Semiconductors, SAA7129HV1 Datasheet - Page 21

• Manufacturer Part Number: SAA7129HV1
• Manufacturer: NXP Semiconductors

Specifications of SAA7129HV1

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 14325
Product data sheet
Table 19:
Table 20:
Table 21:
Bit
7
6
5
4
3
2
1
0
Address Byte
42h, 48h KEY1LU[7:0]
43h, 49h KEY1LV[7:0]
44h, 4Ah KEY1LY[7:0]
Address Byte
45h, 4Bh KEY2LU[7:0]
46h, 4Ch KEY2LV[7:0]
47h, 4Dh KEY2LY[7:0]
KEY1UU[7:0]
KEY1UV[7:0]
KEY1UY[7:0]
KEY2UU[7:0]
KEY2UV[7:0]
KEY2UY[7:0]
Subaddress 3Ah
Subaddresses 42h to 44h and 48h to 4Ah
Subaddresses 45h to 47h and 4Bh to 4Dh
Symbol
CBENB
-
-
SYMP
DEMOFF
CSYNC
MP2C
VP2C
Rev. 03 — 9 December 2004
Description
0 = data from input ports is encoded; default state after reset,
1 = color bar with fixed colors is encoded.
these 2 bits are reserved; each must be set to a logic 0
0 = horizontal and vertical trigger is taken from RCV2 and RCV1,
respectively; default state after reset,
1 = horizontal and vertical trigger is decoded out of ITU-R BT.656
compatible data at MPEG port.
0 = YC
1 = YC
0 = CVBS output signal is switched to CVBS DAC; default state after
reset,
1 = advanced composite sync is switched to CVBS DAC.
0 = input data is twos complement from MPEG port fader input,
1 = input data is straight binary from MPEG port fader input; default state
after reset.
0 = input data is twos complement from video port fader input,
1 = input data is straight binary from video port fader input; default state
after reset.
Description
Key color 1 lower and upper limits for U, V and Y; if MPEG input signal is
within the limits of key color 1 the incoming signals at the video port and
MPEG port are added together according to the equation:
Description
Key color 2 lower and upper limits for U, V and Y; if MPEG input signal is
within the limits of key color 2 the incoming signals at the video port and
MPEG port are added together according to the equation:
FADE1
Default value of all bytes after reset = 80h.
FADE2
Default value of all bytes after reset = 80h.
B
B
C
C
R
R
-to-RGB dematrix is active; default state after reset,
-to-RGB dematrix is bypassed.
video signal + (1
video signal + (1
SAA7128H; SAA7129H
FADE1)
FADE2)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
MPEG signal
LUT values
Digital video encoder
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