SAA7118EEB-T NXP Semiconductors, SAA7118EEB-T Datasheet - Page 33

• Manufacturer Part Number: SAA7118EEB-T
• Description: Video ICs COMPONENT VID DECODER W/COMB F
• Manufacturer: NXP Semiconductors
• Type: Multi-Standard Video Decoderr

Specifications of SAA7118EEB-T

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-700
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Not Compliant
• Other names: SAA7118E/V1,518

NXP Semiconductors
SAA7118_7
Product data sheet
8.1.3 Synchronization
8.1.4 Clock generation circuit
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is
further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the
phase detectors where they are compared with the sub-divided clock frequency. The
resulting output signal is applied to the loop filter to accumulate all phase deviations.
Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to generate the Line Frequency
COntrol (LFCO) signal; see
The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is
also achieved within the synchronization circuit.
The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh.
The internal CGC generates all clock signals required for the video input processor.
The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal
PLL. It is the multiple of the line frequency:
The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including
phase detector, loop filtering, VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50 % duty factor.
Fig 20. CVBS (raw data) range for scaler input, data slicer and X port output
•
•
6.75 MHz = 429
6.75 MHz = 432
a. Sources containing 7.5 IRE black
255
209
71
CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128.
Equation for modification of the raw data levels via bytes RAWG and RAWO:
It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU
Recommendation 601/656” .
level offset (e.g. NTSC M).
60
CVBS
1
LUMINANCE
OUT
SYNC
=
Int
f
f
H
H
Rev. 07 — 7 July 2008
(50 Hz), or
(60 Hz)
RAWG
-----------------
black
black shoulder
sync bottom
white
64
Figure
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Multistandard video decoder with adaptive comb filter
CVBS
21.
nom
–
128
+
255
199
b. Sources not containing black level
60
RAWO
1
offset.
LUMINANCE
SYNC
white
black shoulder = black
sync bottom
SAA7118
© NXP B.V. 2008. All rights reserved.
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