SAF7118EHV1 NXP Semiconductors, SAF7118EHV1 Datasheet - Page 146

• Manufacturer Part Number: SAF7118EHV1
• Manufacturer: NXP Semiconductors

Specifications of SAF7118EHV1

• Screening Level: Industrial
• Package Type: HBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 143. Example of configurations
Table 144. Scaler and interface configuration example
SAF7118_4
Product data sheet
Example
number
1
2
3
4
I
address
(hex)
Global settings
80
83
84
85
86
87
88
Task A: scaler input configuration and output format settings
90
91
92
93
2
C-bus
Main functionality
task enable, IDQ and back-end clock definition
XCLK output phase and X port output enable
IGPH, IGPV, IGP0 and IGP1 output definition
signal polarity control and I port byte swapping
FIFO flag thresholds and video/text arbitration
ICLK and IDQ output phase and I port enable
power save control and software reset
task handling
scaler input source and format definition
reference signal definition at scaler input
I port output formats and configuration
11.5.3 Examples
Scaler source and reference events
analog input to 8-bit I port output, with SAV/EAV codes,
8-bit serial byte stream decoder output at X port;
acquisition trigger at falling edge vertical and rising edge
horizontal reference signal; H and V gates on
IGPH and IGPV, IGP0 = VBI sliced data flag,
IGP1 = FIFO almost full, level
active
analog input to 16-bit output, without SAV/EAV codes,
Y on I port, C
X port; acquisition trigger at falling edge vertical and
rising edge horizontal reference signal; H and V-pulses
on IGPH and IGPV, output FID on IGP0, IGP1 fixed to
logic 1, IDQ qualifier logic 0 active
X port input 8-bit with SAV/EAV codes, no reference
signals on XRH and XRV, XCLK as gated clock; field
detection and acquisition trigger on different events;
acquisition triggers at rising edge vertical and rising edge
horizontal; I port output 8-bit with SAV/EAV codes like
example number 1
X port and H port for 16-bit Y-C
16-bit output selected); XRH and XRV as references;
field detection and acquisition trigger at falling edge
vertical and rising edge horizontal; I port output 8-bit with
SAV/EAV codes, but Y only output
B
-C
R
on H port and decoder output at
B
24, IDQ qualifier logic 1
-C
R
Rev. 04 — 4 July 2008
4 : 2 : 2 input (if no
Multistandard video decoder with adaptive comb filter
Example 1
Hex
10
01
A0
10
45
01
F0
00
08
10
80
Input
window
(pixel)
720
704
720
720
Dec
-
-
-
-
-
-
-
-
-
-
-
240
288
240
288
Example 2
Hex
10
01
C5
09
40
01
F0
00
08
10
40
Dec
-
-
-
-
-
-
-
-
-
-
-
Output
window
(pixel)
720
768
352
200
240
288
288
80
Example 3
Hex
10
00
A0
10
45
01
F0
00
18
10
80
SAF7118
Dec
-
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2008. All rights reserved.
Scale ratios
prsc = 1; fisc = 1;
vsc = 1
prsc = 1;
fisc = 0.91667;
vsc = 1
prsc = 2;
fisc = 1.022;
vsc = 0.8333
prsc = 2;
fisc = 1.8;
vsc = 3.6
Example 4
Hex
10
00
A0
10
45
01
F0
00
38
10
84
146 of 175
Dec
-
-
-
-
-
-
-
-
-
-
-