ISP1507ABS STEricsson, ISP1507ABS Datasheet - Page 55

• Manufacturer Part Number: ISP1507ABS
• Manufacturer: STEricsson

Specifications of ISP1507ABS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 37.
Table 38.
Table 39.
Table 40.
ISP1507A_ISP1507B_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Symbol
-
ID_GND_L
SESS_END_L
SESS_VALID_L
VBUS_VALID_L
HOST_DISCON_L
Symbol
-
LINESTATE1
LINESTATE0
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit allocation
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description
DEBUG - Debug register (address R = 15h) bit allocation
DEBUG - Debug register (address R = 15h) bit description
10.1.10 SCRATCH register
10.1.9 DEBUG register
R
R
7
0
7
0
Remark: It is optional for the link to read this register when the clock is running because
all signal information will automatically be sent to the link through the RXCMD byte.
The bit allocation of this register is given in
The bit allocation of the DEBUG register is given in
current value of signals useful for debugging.
This is an empty register for testing purposes; see
Description
reserved
Line State 1: Contains the current value of LINESTATE 1.
Line State 0: Contains the current value of LINESTATE 0.
reserved
Description
reserved
ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared
when this register is read.
Session End Latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
V
Cleared when this register is read.
Host Disconnect Latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
BUS
R
R
6
0
6
0
Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.
R
R
5
0
5
0
reserved
Rev. 01 — 19 May 2008
ID_GND_L
R
R
4
0
4
0
SESS_
END_L
Table
R
R
3
0
3
0
ISP1507A; ISP1507B
37.
Table
Table
VALID_L
SESS_
41.
ULPI HS USB OTG transceiver
R
R
2
0
39. This register indicates the
2
0
VALID_L
STATE1
VBUS_
LINE
R
R
1
0
1
0
© NXP B.V. 2008. All rights reserved.
DISCON_L
STATE0
HOST_
LINE
R
R
0
0
0
0
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