ISP1507ABS STEricsson, ISP1507ABS Datasheet - Page 23

• Manufacturer Part Number: ISP1507ABS
• Manufacturer: STEricsson

Specifications of ISP1507ABS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1507A_ISP1507B_1
Product data sheet
Fig 6.
DATA[7:0]
REG1V8
REG1V8
V
detector
internal
CLOCK
internal
CC(I/O)
XTAL1
POR
V
NXT
STP
DIR
CC
t1 = V
t2 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive
either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during t
t3 = The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a defined level.
DIR is driven to HIGH and the other pins are driven to LOW.
t4 = The internal PLL is stabilized after t
be stabilized after t
The DIR pin will remain LOW before the link issues a RESET command to the ISP1507.
t5 = The power-up sequence is completed and the ULPI bus interface is ready for use.
Power-up and reset sequence required before the ULPI bus is ready for use
CC
9.3.1 Interface protection
and V
CC(I/O)
t1
By default, the ISP1507 enables a weak pull-up resistor on STP. If the STP pin is
unexpectedly HIGH at any time, the ISP1507 will protect the ULPI interface by enabling
weak pull-down resistors on DATA[7:0].
The interface protect feature prevents unwanted activity of the ISP1507 whenever the
ULPI interface is not correctly driven by the link. For example, when the link powers up
more slowly than the ISP1507.
startup(PLL)
t
PWRUP
are applied to the ISP1507. The ISP1507 regulator starts to turn on.
t2
from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW.
t3
startup(PLL)
t
startup(PLL)
Rev. 01 — 19 May 2008
. If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will
t4
internal clocks stable
RESET command
TXCMD
D
ISP1507A; ISP1507B
internal reset
ULPI HS USB OTG transceiver
PWRUP
.
© NXP B.V. 2008. All rights reserved.
RXCMD
update
004aaa885
bus idle
t5
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