ISP1507ABS STEricsson, ISP1507ABS Datasheet - Page 53

• Manufacturer Part Number: ISP1507ABS
• Manufacturer: STEricsson

Specifications of ISP1507ABS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 30.
Table 31.
Table 32.
ISP1507A_ISP1507B_1
Product data sheet
Bit
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Symbol
DM_PULLDOWN
DP_PULLDOWN
ID_PULLUP
Symbol
-
ID_GND_R
SESS_END_R
SESS_VALID_R
VBUS_VALID_R
HOST_DISCON_
R
OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
description
USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit allocation
USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit description
10.1.5 USB_INTR_EN_R_E register
10.1.6 USB_INTR_EN_F_E register
R/W/S/C
7
0
…continued
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB_INTR_STAT register change from logic 0 to logic 1. By default, all
transitions are enabled.
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB_INTR_STAT register change from logic 1 to logic 0. By default, all
transitions are enabled. See
Description
DM Pull Down: Enables the 15 k pull-down resistor on DM.
0b — Pull-down resistor is not connected to DM.
1b — Pull-down resistor is connected to DM (default).
DP Pull Down: Enables the 15 k pull-down resistor on DP.
0b — Pull-down resistor is not connected to DP.
1b — Pull-down resistor is connected to DP (default).
ID Pull Up: Connects a pull-up to the ID line and enables sampling of the ID level. Disabling
the ID line sampler will reduce PHY power consumption.
0b — Disables sampling of the ID line (default).
1b — Enables sampling of the ID line.
reserved
R/W/S/C
Description
reserved
ID Ground Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on ID_GND.
Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_END.
Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_VLD.
V
A_VBUS_VLD.
Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
HOST_DISCON.
BUS
6
0
Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
R/W/S/C
5
0
Rev. 01 — 19 May 2008
Table 31
ID_GND_R
Table
R/W/S/C
4
1
shows the bit allocation of the register.
33.
R/W/S/C
END_R
SESS_
3
1
ISP1507A; ISP1507B
VALID_R
R/W/S/C
SESS_
ULPI HS USB OTG transceiver
2
1
VALID_R
R/W/S/C
VBUS_
1
1
© NXP B.V. 2008. All rights reserved.
DISCON_R
R/W/S/C
HOST_
0
1
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