ISP1507ABS STEricsson, ISP1507ABS Datasheet - Page 18

• Manufacturer Part Number: ISP1507ABS
• Manufacturer: STEricsson

Specifications of ISP1507ABS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 5.
Table 6.
ISP1507A_ISP1507B_1
Product data sheet
Signal
Reserved
INT
Reserved
Signal
TX_ENABLE
TX_DAT
TX_SE0
INT
RX_DP
RX_DM
RX_RCV
Reserved
Signal mapping during low-power mode
Signal mapping for 6-pin serial mode
8.1.3 6-pin full-speed or low-speed serial mode
8.1.4 3-pin full-speed or low-speed serial mode
Maps to
DATA2
DATA3
DATA[7:4]
Maps to
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1507 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0]
bus definition changes to that shown in
the 6PIN_FSLS_SERIAL bit in the INTF_CTRL register (see
exit 6-pin serial mode, the link asserts STP. This is provided primarily for links that contain
legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path
to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1 .
If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1507 to 3-pin serial mode. In 3-pin serial mode, the data bus
definition changes to that shown in
3PIN_FSLS_SERIAL bit in the INTF_CTRL register (see
3-pin serial mode, the link asserts STP. This is primarily provided for links that contain
legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path
to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1 .
Direction
O
O
O
Direction
I
I
I
O
O
O
O
O
Description
reserved; the ISP1507 will drive this pin to LOW
active HIGH interrupt indication; will be asserted whenever any unmasked
interrupt occurs
reserved; the ISP1507 will drive these pins to LOW
Description
active HIGH transmit enable
transmit differential data on DP and DM
transmit single-ended zero on DP and DM
active HIGH interrupt indication; will be asserted whenever any
unmasked interrupt occurs
single-ended receive data from DP
single-ended receive data from DM
differential receive data from DP and DM
reserved; the ISP1507 will drive this pin to LOW
Rev. 01 — 19 May 2008
…continued
Table
Table
7. To enter 3-pin serial mode, the link sets the
ISP1507A; ISP1507B
6. To enter 6-pin serial mode, the link sets
Section
ULPI HS USB OTG transceiver
Section
10.1.3) to logic 1. To exit
10.1.3) to logic 1. To
© NXP B.V. 2008. All rights reserved.
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