AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 265

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

Am79C975 EEPROM Map
The Am79C975 PCnet-FAST III controller uses an ex-
tended EEPROM map compared to the Am79C973 de-
vice (locations reserved in Am79C973 EEPROM map),
Note: * Lowest EEPROM address.
Word
Addr.
00h*
0Ah
0Bh
0Ch
0Dh
0Eh
1Ah
1Bh
1Ch
1Dh
1Eh
3Eh
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
3Fh
Addr.
Byte
0Bh
0Dh
0Fh
1Bh
1Dh
1Fh
2Bh
2Dh
2Fh
3Bh
3Dh
3Fh
4Bh
4Dh
4Fh
7Dh
7Fh
01h
03h
05h
07h
09h
11h
13h
15h
17h
19h
21h
23h
25h
27h
29h
31h
33h
35h
37h
39h
41h
43h
45h
47h
49h
51h
2nd byte of the ISO 8802-3 (IEEE/ANSI 802.3)
station physical address for this node
4th byte of the node address
6th byte of the node address
CSR116[15:8] (OnNow Misc. Config).
Hardware ID: must be 11h if compatibility to
AMD drivers is desired
User programmable space
MSB of two-byte checksum, which is the sum of
bytes 00h-0Bh and bytes 0Eh and 0Fh
Must be ASCII “W” (57h) if compatibility to AMD
driver software is desired
BCR2[15:8] (Miscellaneous Configuration)
BCR4[15:8] (Link Status LED)
BCR5[15:8] (LED1 Status)
BCR6[15:8] (LED2 Status)
BCR7[15:8] (LED3 Status)
BCR9[15:8] (Full-Duplex Control)
BCR18[15:8] (Burst and Bus Control)
BCR22[15:8] (PCI Latency)
BCR23[15:8] (PCI Subsystem Vendor ID)
BCR24[15:8] (PCI Subsystem ID)
BCR25[15:8] (SRAM Size)
BCR26[15:8] (SRAM Boundary)
BCR27[15:8] (SRAM Interface Control)
BCR32[15:8] (MII Control and Status)
BCR33[15:8] (MII Address)
BCR35[15:8] (PCI Vendor ID)
BCR36[15:8] (Conf. Sp. byte 43h alias)
BCR37[15:8] (DATA_SCALE alias0)
BCR38[15:8] (DATA_SCALE alias 1)
BCR39[15:8] (DATA_SCALE alias 2)
BCR40[15:8] (DATA_SCALE alias 3)
BCR41[15:8] (DATA_SCALE alias 4)
BCR42[15:8] (DATA_SCALE alias 5)
BCR43[15:8] (DATA_SCALE alias 6)
BCR44[15:8] (DATA_SCALE alias 7)
BCR48[15:8] N_IP_ADR[15:8]
BCR49[15:8] N_IP_ADR[31:24]
BCR50[15:8] M_IEEE_ADR[15:8]
BCR51[15:8] M_IEEE_ADR[31:24]
BCR52[15:8] M_IEEE_ADR[47:40]
BCR53[15:8] M_IP_ADR[15:8]
BCR54[15:8] M_IP_ADR[31:24]
Checksum adjust byte for the 82 bytes of the
EEPROM contents, checksum of the 82 bytes of
the EEPROM should total to FFh
Reserved for Boot ROM usage
Reserved for Boot ROM usage
Most Significant Byte
P R E L I M I N A R Y
Am79C973/Am79C975
since there are some new registers in the SMIU that
are loaded from the EEPROM.
Addr.
Byte
0Ah
0Ch
0Eh
1Ah
1Ch
1Eh
2Ah
2Ch
2Eh
3Ah
3Ch
3Eh
4Ah
4Ch
4Eh
7Ch
7Eh
00h
02h
04h
06h
08h
10h
12h
14h
16h
18h
20h
22h
24h
26h
28h
30h
32h
34h
36h
38h
40h
42h
44h
46h
48h
50h
First byte of the ISO 8802-3 (IEEE/ANSI 802.3)
station physical address for this node, where
“first byte” refers to the first byte to appear on
the 802.3 medium
3rd byte of the node address
5th byte of the node address
CSR116[7:0] (OnNow Misc. Config.)
Reserved location: must be 00h
User programmable space
LSB of two-byte checksum, which is the sum of
bytes 00h-0Bh and bytes 0Eh and 0Fh
Must be ASCII “W” (57h) if compatibility to AMD
driver software is desired
BCR2[7:0] (Miscellaneous Configuration)
BCR4[7:0] (Link Status LED)
BCR5[7:0] (LED1 Status)
BCR6[7:0] (LED2 Status)
BCR7[7:0] (LED3 Status)
BCR9[7:0] (Full-Duplex Control)
BCR18[7:0] (Burst and Bus Control)
BCR22[7:0] (PCI Latency)
BCR23[7:0] (PCI Subsystem Vendor ID)
BCR22[7:0] (PCI Subsystem ID)
BCR25[7:0] (SRAM Size)
BCR26[7:0] (SRAM Boundary)
BCR27[7:0] (SRAM Interface Control)
BCR32[7:0] (MII Control and Status)
BCR33[7:0] (MII Address)
BCR35[7:0] (PCI Vendor ID)
BCR36[7:0] (Conf. Sp. byte 42h alias)
BCR37[7:0] (Conf. Sp. byte 47h0 alias)
BCR38[7:0] (Conf. Sp. byte 47h1 alias)
BCR39[7:0] (Conf. Sp. byte 47h2 alias)
BCR40[7:0] (Conf. Sp. byte 47h3 alias)
BCR41[7:0] (Conf. Sp. byte 47h4 alias)
BCR42[7:0] (Conf. Sp. byte 47h5 alias)
BCR43[7:0] (Conf. Sp. byte 47h6 alias)
BCR44[7:0] (Conf. Sp. byte 47h7 alias)
BCR48[7:0] N_IP_ADR[7:0]
BCR49[7:0] N_IP_ADR[23:16]
BCR50[7:0] M_IEEE_ADR[7:0]
BCR51[7:0] M_IEEE_ADR[23:16]
BCR52[7:0] M_IEEE_ADR[39:32]
BCR53[7:0] M_IP_ADR[7:0]
BCR54[7:0] M_IP_ADR[23:16]
BCR55[7:0] SMIU Slave Address
Reserved for Boot ROM usage
Reserved for Boot ROM usage
Least Significant Byte
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