AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 253

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

The host must load the Receive Pattern RAM using
one or multiple Block Write commands to the Receive
Pattern RAM Data port. The command code of the
Block Write command must be set to 34, the address
of the Receive Pattern RAM Data port. The byte count
field can have any value since it is ignored by the
Am79C975 controller. The device is capable of receiv-
ing any amount of frame filter bytes even passed the
limit of 32 bytes as defined by the SMB specification.
The location within the Receive Pattern RAM where the
next byte is written to is controlled by the Receive Pat-
tern RAM Address register (MRX_PADR). This register
will come up cleared to 0 after H_RESET. With every
byte write the address register will auto-increment. This
allows a FIFO-type access to the Receive Pattern RAM
and the host does not need to keep track of the location
he is writing to. In addition, MRX_PADR can be set to
any address within the Receive Pattern RAM in order
to modify a specific location. The sequence the Re-
ceive Pattern RAM must be written is LSB (bits 7:0) of
the first pattern word, followed by bits 15:8 of the first
Once the acknowledgment frame filter has been loaded
to the Receive Pattern RAM, the host must set the
MRX_ENABLE bit in the Receive Status register to en-
able the reception of acknowledgment frames.
When an incoming frame passes the acknowledgment
frame filter, the Am79C975 controller will store the
frame data in the Receive Data memory. Runt frames
(frames shorter than 64 bytes) are automatically de-
leted, unless MRX_RPA (bit 2 in the SMIU Command
register) is set to a 1. If the incoming frame is larger
than 128 bytes (including FCS), the Am79C975 con-
troller will only store the first 128 bytes and discard the
rest. A message length between 129 and 132 bytes in-
dicates that only FCS bytes have been lost and all mes-
sage data bytes are available in the Receive Data
Frame
Offset
12
16
20
24
28
32
36
40
0
4
8
Offset +
E0
00
08
xx
xx
xx
xx
xx
xx
xx
c7
0
Offset +
1B
00
06
01
48
xx
xx
xx
xx
xx
xx
1
Offset +
1A
9d
xx
xx
xx
xx
xx
xx
xx
xx
xx
2
Offset +
00
37
xx
xx
xx
xx
xx
xx
xx
xx
xx
3
P R E L I M I N A R Y
Am79C973/Am79C975
Word
RAM
1
2
3
4
5
6
EOP
pattern word. The first pattern word is followed by the
second pattern word. The host need not write all 8 pat-
tern words. The last pattern word must have the EOP
bit set, even if the pattern word number 8 is the last
one. Words following the EOP bit are ignored. The host
must make sure that no more than 40 bytes are written
to the Receive Pattern RAM. When MRX_ENABLE is
set to 1, the MRX_PADR register will clear to 0 and no
write to the Receive Pattern RAM may occur. A new ac-
knowledgment frame filter can be written to the Re-
ceive Pattern RAM after disabling the receiver by
setting MRX_ENABLE to 0.
The table below shows how a sample pattern would be
stored in the Receive Pattern RAM. Note that in the 4
columns containing the frame data, the byte in the left-
most column is closer to the start of the frame than the
byte in the rightmost column. The 4 columns showing
pattern data stored in the RAM show the least signifi-
cant byte of the RAM word in the rightmost column.
memory. A message length greater than 132 indicates
that message data bytes have been lost from the end
of the message. The Receive Message Length register
(MRX_LEN) will indicate the correct message length
up to 255 bytes. It will freeze at 255 for longer frames.
Pad stripping is not supported by the SMIU. The setting
of the ASTRP_RCV bit in CSR4 only effects the recep-
tion of normal frames and not of acknowledgment
frames. Note that if the main receiver of the Am79C975
device is enabled, the acknowledgment frame will also
be passed up to the network driver and from there to
the protocol stack. The frame format of the acknowl-
edgment frame should be designed such that it will be
identified by the protocol stack as a special frame and
thrown away. There will be no real performance impact
0
0
0
0
0
1
Skip
0
0
1
1
3
0
Mask
1111
0011
0011
0010
1100
0011
00
37
xx
xx
xx
xx
1A
xx
xx
xx
9d
xx
Pattern
1B
00
06
01
xx
48
E0
00
08
xx
xx
c7
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