AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 121

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

PCI Power Management Capabilities Register
(PMC)
Offset 42h
Note: All bits of this register are loaded from
EEPROM. The register is aliased to BCR36 for testing
purposes.
Bit
15-11
10
9
Name
PME_SPT
D2_SPT
D1_SPT
cates the power states in which
the function may assert PME. A
value of 0b for any bit indicates
that the function is not capable of
asserting the PME signal while in
that power state.
asserted from D0.
asserted from D1.
asserted from D2.
asserted from D3hot.
asserted from D3cold.
cates that the controller is capa-
ble of generating PME from the
D3 cold state. This capability de-
pends on the presence of auxilia-
ry power, as indicated by the
AUXDET input. The capability
can be disabled by loading a zero
into bit 15 of BCR36 from the EE-
PROM. (This register is aliased to
the PMC register.)
function supports the D2 Power
Management State.
function supports the D1 Power
Management State.
Description
PME Support. This 5-bit field indi-
Bit(11) XXXX1b - PME can be
Bit(12) XXX1Xb - PME can be
Bit(13) XX1XXb - PME can be
Bit(14) X1XXXb - PME can be
Bit(15) 1XXXXb - PME can be
Read only.
Bit 15 of the PMC register indi-
D2 Support. If this bit is a 1, this
Read only.
D1 Support. If this bit is a 1, this
Read only.
P R E L I M I N A R Y
Am79C973/Am79C975
8-6
5
4
3
2-0
PCI Power Management Control/Status Register
(PMCSR)
Offset 44h
Bit
15
PME_STATUS PME Status. This bit is set when
RES
DSI
RES
PME_CLK
PMIS_VER Power Management Interface
Name
Reserved locations. Written as
zeros and read as undefined.
Device
When this bit is 1, it indicates that
special initialization of the func-
tion is required (beyond the stan-
dard PCI configuration header)
before the generic class device
driver is able to use it.
Read only.
Reserved locations. Written as
zeros and read as undefined.
PME Clock. When this bit is a 1,
it indicates that the function relies
on the presence of the PCI clock
for PME operation. When this bit
is a 0 it indicates that no PCI
clock is required for the function
to generate PME.
Functions that do not support
PME generation in any state
must return 0 for this field.
Read only.
Specification Version. A value of
001b indicates that this function
complies with the revision 1.1 of
the PCI Power Management In-
terface Specification.
Description
the function would normally as-
sert the PME signal independent
of the state of the PME_EN bit.
Writing a 1 to this bit will clear it
and cause the function to stop as-
serting a PME (if enabled). Writ-
ing a 0 has no effect.
If the function supports PME from
D3cold then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating system is initially load-
ed.
Specific
Initialization.
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