S2004TB Applied Micro Circuits Corporation, S2004TB Datasheet - Page 14

• Manufacturer Part Number: S2004TB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S2004TB

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

CHANNEL LOCKING/RE-LOCKING
PROCEDURE
The Channel locking/relocking procedures are sum-
marized below. Following these procedures will in-
sure proper CHANNEL LOCK operation of the
device. When powered up, the S2004 will lock to the
received data within approximately 2500 bit times.
The CRU must report lock for approximately 32,000
REFCLK periods (320 s) before channel locking is
enabled.
1. Insure that the S2004 is in the “No Sync” state.
2. Transmit the appropriate synchronization se-
3. Wait for “channel lock detected” as defined by
The S2004 will enter the “No Sync” state if: any CRU
loses lock, if the CH_LOCK signal is de-asserted, if
four or more consecutive decoder errors are ob-
served, or if the decoder error rate exceeds 50% in a
block of 16 bytes, or if TCLKD is low. If desired, the
CRU lock status of each channel can be checked by
de-asserting CH_LOCK and confirming that “Loss of
Sync” status (Table 7) is not reported by any chan-
nel. To reacquire Sync after moving to the “No Sync”
state, repeat steps 2 and 3 above.
8B/10B Decoding
After serial to parallel conversion, the S2004 pro-
vides 8B/10B decoding of the data. The received 10-
bit code word is decoded to recover the original 8-bit
data. The decoder also checks for errors and flags,
either invalid code word errors or running disparity
errors by assertion of the ERRx signal. Error type is
determined by examining the EOF output in accor-
dance with Table 7. When more than one reportable
condition occurs simultaneously, reporting is in ac-
cordance with the rank assigned by Table 7.
14
S2004
This can be accomplished by resetting the device
by toggling TCLKD low, or by de-asserting the
channel lock for several clock periods and then
re-asserting.
quence. Four K28.5 characters or the 16 word
SYNC sequence can be used to de-skew the
DOUT FIFOs. The 16 word SYNC character can
be generated by asserting SYNC=1 and DN=1.
Table 7.
Data Output
Data is output on the DOUT[0:7] outputs. K-characters
are flagged using the KFLAG signal. The EOF (with
KFLAG) is used to indicate the reception of a valid
K28.5 character. Invalid codewords and decoding er-
rors are indicated on the ERR output. KFLAG, EOF,
and ERR are buffered with the data in the FIFO to
insure that all outputs are synchronized at the S2004
outputs. Errors are reported independently for each
channel in both CHANNEL-LOCK mode and NOR-
MAL mode operation.
The S2004 TTL outputs are optimized to drive 65
line impedances. Internal source matching provides
good performance on unterminated lines of reason-
able length.
Parallel Output Clock Rate
Two output clock modes are supported, as shown in
Table 8. When CMODE is High, a complementary
TTL clock at the data rate is provided on the RCxP/N
outputs. Data should be clocked on the rising edge
of RCxP. When CMODE is Low, a complementary
TTL clock at 1/2 the data rate is provided. Data
should be latched on the rising edge of RCxP and
the rising edge of RCxN.
In Fibre Channel and Gigabit Ethernet applications,
multiple consecutive K28.5 characters cannot be
generated. However, for serial backplane applica-
tions this can occur. The S2004 must be able to
operate properly when multiple K28.5 characters are
received. After the first K28.5 is detected and
aligned, the RCxP/N clock will operate without
glitches or loss of cycles.
Receiver Output Clocking
The S2004 parallel output clock source is deter-
mined by the TMODE selection. When REFCLK
clocking is selected (TMODE = Low), the parallel
output clocks (RCxP/N) are sourced from the TCLKA
input. When TCLK clocking is selected (External
Clocking Mode), the parallel output clocks are de-
rived from the recovered clock from each channel.
Table 8A describes the receiver output clocking op-
tions available.
QUAD SERIAL BACKPLANE DEVICE
October 10, 2000 / Revision D