S2004 Applied Micro Circuits Corporation, S2004 Datasheet
S2004
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S2004 Summary of contents
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... The chip requires a 3.3V power supply and dissi- pates 2.5 watts. Figure 1 shows the S2004 and S2204 in a Gigabit Ethernet application. Figure 2 combines the S2004 with a crosspoint switch to demonstrate a serial backplane application. Figure 3 is the input/output diagram ...
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... QUAD SERIAL BACKPLANE DEVICE Crosspoint Switch S2016 S2025 BACKPLANE SIGNAL GROUP MAC (ASIC) MAC ATM (ASIC) Fibre S2004 Channel MAC Ethernet (ASIC) Etc. MAC (ASIC) MAC (ASIC) MAC ATM (ASIC) Fibre S2004 Channel MAC Ethernet (ASIC) Etc. MAC (ASIC) January 29, 2002 / Revision E ...
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... QUAD SERIAL BACKPLANE DEVICE Figure 3. S2004 Input/Output Diagram RESET RATE REFCLK CLKSEL TMODE TCLKO SYNC DINA[0:7] 10 DNA, KGENA TCLKA DINB[0:7] 10 DNB, KGENB TCLKB DINC[0:7] 10 DNC, KGENC TCLKC DIND[0:7] 10 DND, KGEND TCLKD ERRA DOUTA[0:7] 10 EOFA, KFLAGA RCA P/N ERRB DOUTB[0:7] 10 EOFB, KFLAGB RCB P/N ...
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... S2004 Figure 4. Transmitter Block Diagram RATE REFCLK CLKSEL CH_LOCK TMODE 8 DINA[0:7] FIFO SYNC (input) DNA KGENA TCLKA 8 DINB[0:7] FIFO (input) DNB KGENB TCLKB 8 DINC[0:7] FIFO (input) DNC KGENC TCLKC 8 DIND[0:7] FIFO (input) DND KGEND ...
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... Parallel Stretching Timing 8B/10B Decode DOUT CRU 8 10 Framing Serial- Data Parallel Stretching Timing 8B/10B Decode DOUT CRU 8 Framing 10 Serial- Data Parallel Stretching Timing S2004 TXABP RXAP RXAN LPENA TXBBP RXBP RXBN LPENB TXCBP RXCP RXCN LPENC TXDBP RXDP RXDN LPEND 5 ...
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... REFCLK. Figure 6 demonstrates the flexibility afforded by the S2004. A low jitter reference is provided directly to the S2004 at either 1/10 or 1/20 the serial data rate. This insures minimum jitter in the synthesized clock used for serial data transmission. A system clock output at the parallel word rate, TCLKO, is derived from the PLL and provided to the upstream circuit as a system clock ...
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... Gigabit Ethernet applications and is illustrated in Fig- ure 7. Half Rate Operation The S2004 supports full and 1/2 rate operation for all modes of operation. When RATE is LOW, the S2004 serial data rate equals the VCO frequency. When RATE is HIGH, the VCO is divided-by-2 before being provided to the chip ...
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... Frequency Synthesizer (PLL) The S2004 synthesizes a serial transmit clock from the reference signal. Upon startup, the S2004 will obtain phase and frequency lock within 2500 bit times after the start of receiving reference clock in- puts. Reliable locking of the transmit PLL is assured, but a lock-detect output is NOT provided ...
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... In addition to path length induced timing skew, the S2004 can tolerate up to tween channels after deskewing the outputs. Test Functions The S2004 can be configured for factory test to aid in functional testing of the device. When in the test mode, the internal transmit and receive voltage-con- e ...
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... This allows the VCO to maintain the cor- rect frequency in the absence of data. The ‘lock to reference’ frequency criteria insure that the S2004 will respond to variations in the serial data input frequency (compared to the reference fre- quency). The new Lock State is dependent upon the current lock state, as shown in Table 6 ...
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... The “In Sync” state is reported for each as 0-1-0. Once the S2004 has entered the “In Sync” state, it will report status but will not alter the relative skew of the output FIFOs. The S2004 will exit the “In Sync” state and move to the “ ...
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... S2004 Figure 8. Channel Lock State Machine All four channels in Re-Sync with valid data within deskew window RE-SYNC Figure 9. Channel Lock Synchronization Timing (Internal) RESYNC A (Internal) RESYNC B (Internal) RESYNC C (Internal) RESYNC D (internal) deskewed RESYNC A (internal) deskewed RESYNC B (internal) deskewed RESYNC C (internal) deskewed RESYNC D ...
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... The CRU must report lock for approximately 32,000 REFCLK periods (320 s) before channel locking is enabled. 1. Insure that the S2004 is in the “No Sync” state. This can be accomplished by resetting the device by toggling TCLKD low de-asserting the channel lock for several clock periods and then re-asserting ...
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... The recommended clocking configuration for exter- nal clocking mode (REFCLK input clocking) is shown in Figure 10. TCLKA is sourced from TCLKO, which is frequency locked to the Reference clock input. Table 8A. S2004 Data Clocking ...
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... LPEN. TEST MODES The S2004 has a testability input to aid in functional testing of the device. The test mode is entered when CH_LOCK is HIGH and TCLKB is HIGH. Thus users must take care to insure that TCLKB is held LOW when operating in the channel locked mode ...
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... S2004 Table 9. JTAG Pin Assignments (Continued ...
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... S2004 Table 10. Transmitter Signal Descriptions (Continued ...
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... S2004 Table 13. Receiver Output Pin Assignment and Descriptions ...
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... S2004 Table 14. Receiver Input Pin Assignment and Descriptions ...
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... S2004 Table 17. JTAG Test Signals QUAD SERIAL BACKPLANE DEVICE ...
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... QUAD SERIAL BACKPLANE DEVICE Figure 12. S2004 Pinout (Bottom View ...
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... S2004 Figure 13. S2004 Pinout (Top View ...
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... QUAD SERIAL BACKPLANE DEVICE Figure 14. Compact 23mm x 23mm 208 TBGA Package Thermal Management January 29, 2002 / Revision ˚ S2004 ˚ ...
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... All AC measurements are made from the reference voltage levels of the clock (1.4V) to the valid input or output data levels (.8V or 2.0V). Figure 16. Transmitter Timing (Normal or Channel Lock Mode, TMODE = 1) TCLKx, TCLKA DINx[0:7], DNx, KGENx, SYNC SERIAL DATA OUT Table 19. S2004 Transmitter Timing (Normal or Channel Lock Mode, TMODE = ...
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... QUAD SERIAL BACKPLANE DEVICE Table 20. S2004 Receiver Timing (Full and Half Clock Mode ...
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... S2004 Figure 17. Receiver Timing (Full Clock Mode, CMODE = 1) SERIAL DATA IN RCxN RCxP DOUTx[0:7], EOFx, KFLAGx, ERRx Figure 18. Receiver Timing (Half Clock Mode, CMODE = 0, TMODE = 1) SERIAL DATA IN RCxN RCxP DOUTx[0:7], EOFx, KFLAGx, ERRx Figure 19. Receiver Timing (External Clock Mode) (TCLKA to DATA Propagation Delay, TMODE = 0) ...
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... QUAD SERIAL BACKPLANE DEVICE Figure 20. TCLKO Timing REFCLK TCLKO Table 22. S2004 Transmitter (TCLKO Timing Note: Measurements are made at 1.4V level of clocks. January 29, 2002 / Revision ...
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... S2004 Table 23. Absolute Maximum Ratings ...
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... OUTPUT LOAD The S2004 serial outputs do not require output pulldown resistors. ACQUISITION TIME With the input eye diagram shown in Figure 26, the S2004 will recover data with a 1E-9 BER within the time specified Table 27 after an instanta- LOCK neous phase shift of the incoming data. ...
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... QUAD SERIAL BACKPLANE DEVICE Figure 27. Loop Filter Capacitor Connections January 29, 2002 / Revision E 270 CAP1 22 nf CAP2 270 S2004 S2004 37 ...
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... S2004 Ordering Information Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...