XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 4

• Manufacturer Part Number: XR16L570IL24-F
• Description: 2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
• Manufacturer: Exar Corporation

Specifications of XR16L570IL24-F

• Features: *
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Protocol: RS232, RS422
• Voltage - Supply: 1.62 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
N
PwrSave
ANCILLARY SIGNALS
RESET
XTAL1
XTAL2
OTE
(CLK)
N
VCC
GND
GND
CD#
RI#
AME
: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
24-QFN
Center
P
Pad
17
19
10
IN
8
7
-
-
-
#
32-QFN
Center
P
Pad
26
27
10
23
28
13
11
IN
-
#
T
Pwr
Pwr
Pwr
YPE
O
I
I
I
I
I
UART Carrier-Detect (active low) or general purpose input. This input should be con-
nected to VCC when not used. This input has no effect on the UART. This pin is not
available in the 24-QFN package.
UART Ring-Indicator (active low) or general purpose input. This input should be con-
nected to VCC when not used. This input has no effect on the UART. This pin is not
available in the 24-QFN package.
Crystal or external clock input. This input is not 5V tolerant.
Crystal or buffered clock output. This output may be use to drive a clock buffer which
can drive other device(s). This pin is not available in the 24-QFN package.
Power-Save (active high). This feature isolates the L570’s data bus interface from
the host preventing other bus activities that cause higher power drain during sleep
mode. See Sleep Mode with Auto Wake-up and Power-Save Feature section for
details. This pin is not available in the 28-QFN package.
This input is the active high RESET signal.
A 40 ns minimum active pulse on this pin will reset the internal registers and all out-
puts of the UART. The UART transmitter output will be held at logic 1, the receiver
input will be ignored and outputs are reset during reset period (see UART Reset Con-
ditions).
1.62V to 5.5V power supply. All input pins, except CLK, are 5V tolerant.
Power supply common, ground.
The center pad on the backside of the QFN packages is metallic and should be con-
nected to GND on the PCB. The thermal pad size on the PCB should be the approxi-
mate size of this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
4
D
ESCRIPTION
REV. 1.0.1