XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 33
XR16L570IL24-F
Manufacturer Part Number
XR16L570IL24-F
Description
2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
Manufacturer
Exar Corporation
Datasheet
1.XR16L570IL32TR-F.pdf
(47 pages)
Specifications of XR16L570IL24-F
Features
*
Number Of Channels
1, UART
Fifo's
16 Byte
Protocol
RS232, RS422
Voltage - Supply
1.62 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
24-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR16L570IL24-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
REV. 1.0.1
EFR[5]: Special Character Detect Enable
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•
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at one trigger level above the programmed trigger level. RTS# will return to a logic
0 when FIFO data falls below one trigger level below the programmed trigger level. The RTS# output must be
asserted (logic 0) before the auto RTS can take effect. RTS# pin will function as a general purpose output
when hardware flow control is disabled.
•
•
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
•
•
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, refer to
4.16
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Write Only
“Section 2.15, Auto Xon/Xoff (Software) Flow Control” on page
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
33
15.
XR16L570