XR16L570IL24-F Exar Corporation, XR16L570IL24-F Datasheet - Page 32

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XR16L570IL24-F

Manufacturer Part Number
XR16L570IL24-F
Description
2.25 To 5.5V W/ 5V TOLERANT INPUT UART W/16 BYTE FIFO W/ POWER SAVE
Manufacturer
Exar Corporation
Datasheet

Specifications of XR16L570IL24-F

Features
*
Number Of Channels
1, UART
Fifo's
16 Byte
Protocol
RS232, RS422
Voltage - Supply
1.62 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
24-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR16L570IL24-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2, 5, 6 and 7
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
4.15
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 2, 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 2, 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR
C
ONT
X
X
X
0
0
1
0
1
1
0
1
0
BIT
Enhanced Feature Register (EFR)
-3
-3
EFR
C
ONT
X
X
X
0
0
0
1
1
0
1
1
0
BIT
-2
-2
T
ABLE
EFR
C
ONT
10: S
X
X
X
X
0
0
1
0
1
1
1
1
BIT
-1
-1
OFTWARE
Table
EFR
C
ONT
10). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
X
X
X
X
0
0
0
1
1
1
1
1
F
BIT
LOW
32
-0
-0
C
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1, Xoff1
Receiver compares Xon2, Xoff2
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
ONTROL
T
RANSMIT AND
F
UNCTIONS
R
ECEIVE
S
OFTWARE
F
LOW
C
REV. 1.0.1
ONTROL

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