UJA1069TW24/5V0/C: NXP Semiconductors, UJA1069TW24/5V0/C: Datasheet - Page 26

• Manufacturer Part Number: UJA1069TW24/5V0/C:
• Description: UJA1069TW24/HTSSOP24/REEL13DP/
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/5V0/C:

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935285413518

NXP Semiconductors
Table 4.
[1]
[2]
UJA1069_4
Product data sheet
Bit
15 and 14
13
12
11 to 6
5 to 3
2
1
0
Flash mode can be entered only with the watchdog service sequence ‘Normal mode to Flash mode to Normal mode to Flash mode’,
while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up
mode to prepare the microcontroller for flash memory download. The four RSS bits in the System Status register reflect the reset source
information, confirming the Flash entry sequence. By using the Initializing Flash mode (within t
now successfully enter Flash mode.
See
Section
Mode register bit description (bits 15 to 12 and 5 to 0)
Symbol
A1, A0
RRS
RO
NWP[5:0]
OM[2:0]
SDM
EN
-
6.13.1.
Description
register address
Read Register
Select
Read Only
see
Operating Mode
Software
Development
Mode
Enable
reserved
Table 5
Value
00
1
0
1
0
001
010
011
100
101
110
111
1
0
1
0
0
Rev. 04 — 28 October 2009
Function
select Mode register
read System Diagnosis register
read System Status register
read selected register without writing to Mode register
read selected register and write to Mode register
Normal mode
Standby mode
initialize Flash mode
Sleep mode
initialize Normal mode
leave Flash mode
Flash mode
Software development mode enabled
normal watchdog, interrupt, reset monitoring and fail-safe
behavior
EN output pin HIGH
EN output pin LOW
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
[1]
[1]
LIN fail-safe system basis chip
WD(init)
after system reset) the SBC will
[2]
UJA1069
© NXP B.V. 2009. All rights reserved.
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