UJA1069TW24/5V0/C: NXP Semiconductors, UJA1069TW24/5V0/C: Datasheet - Page 13

• Manufacturer Part Number: UJA1069TW24/5V0/C:
• Description: UJA1069TW24/HTSSOP24/REEL13DP/
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/5V0/C:

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935285413518

NXP Semiconductors
UJA1069_4
Product data sheet
6.4.1 Watchdog start-up behavior
6.4.2 Watchdog window behavior
Following any reset event the watchdog is used to monitor the ECU start-up procedure. It
observes the behavior of the RSTN pin for any clamping condition or interrupted reset
wire. In case the watchdog is not properly served within t
and the monitoring procedure is restarted. In case the watchdog is again not properly
served, the system enters Fail-safe mode (see also
mode).
Whenever the SBC enters Normal mode, the Window mode of the watchdog is activated.
This ensures that the microcontroller operates within the required speed; a too fast as well
as a too slow operation will be detected. Watchdog triggering using the Window mode is
illustrated in
The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler.
The period can be changed within any valid trigger window. Whenever the watchdog is
triggered within the window time, the timer will be reset to start a new period.
The watchdog window is defined to be between 50 % and 100 % of the nominal
programmed watchdog period. Any too early or too late watchdog access or wrong Mode
register code access will result in an immediate system reset, entering Start-up mode.
Fig 5.
trigger
via SPI
Watchdog triggering using Window mode
Figure
trigger point
last
5.
trigger
restarts
period
Rev. 04 — 28 October 2009
too early
(with different duration if
trigger restarts period
earliest possible
trigger point
period
50 %
desired)
trigger
via SPI
trigger window
Figure
too early
latest possible
trigger point
LIN fail-safe system basis chip
WD(init)
100 %
new period
possible
earliest
trigger
4, Start-up mode and Restart
50 %
point
, another reset is forced
window
trigger
possible
trigger
latest
100 %
point
UJA1069
© NXP B.V. 2009. All rights reserved.
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