STM8AF6246TCSSSY STMicroelectronics, STM8AF6246TCSSSY Datasheet - Page 54
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STM8AF6246TCSSSY
Manufacturer Part Number
STM8AF6246TCSSSY
Description
8 BITS MICROCONTR
Manufacturer
STMicroelectronics
Series
STM8Ar
Datasheet
1.STM8AF5289TCY.pdf
(106 pages)
Specifications of STM8AF6246TCSSSY
Core Processor
STM8A
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8AF6246TCSSSY
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM8AF6246TCSSSY
Manufacturer:
ST
Quantity:
20 000
Option bytes
54/106
Table 20.
Option byte no.
OPT0
OPT1
OPT2
Option byte description
ROP[7:0]: Memory readout protection (ROP)
UBC[7:0]: User boot code area
AFR7: Alternate function remapping option 7
AFR6: Alternate function remapping option 6
AFR5: Alternate function remapping option 5
AFR4: Alternate function remapping option 4
AFR3: Alternate function remapping option 3
AFR2: Alternate function remapping option 2
AFR1: Alternate function remapping option 1
AFR0: Alternate function remapping option 0
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the STM8A microcontroller family reference manual
(RM0016) section on Flash/EEPROM memory readout protection for
details.
0x00: No UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03 to 0xFF: Pages 4 to 255 defined as UBC, memory write-protected
Note: Refer to the STM8A microcontroller family reference manual
(RM0016) section on Flash/EEPROM write protection for more details.
0: Port D4 alternate function = TIM2_CH1
1: Port D4 alternate function = BEEP
0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I
I
0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,
port B1 alternate function = AIN1, port B0 alternate function = AIN0.
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate
function = TIM1_CH1N.
0: Port D7 alternate function = TLI
1: Reserved
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = TIM1_BKIN
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = CLK_CCO
Note: AFR2 option has priority over AFR3 if both are activated
0: Port A3 alternate function = TIM2_CH3, port D2 alternate function
TIM3_CH1.
1: Port A3 alternate function = TIM3_CH1, port D2 alternate function
TIM2_CH3.
0: Port D3 alternate function = TIM2_CH2
1: Port D3 alternate function = ADC_ETR
2
C_SCL.
Doc ID 14395 Rev 8
Description
2
C_SDA, port B4 alternate function =
STM8AF52/62xx, STM8AF51/61xx